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HM-6508883 Dataheets PDF



Part Number HM-6508883
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description 1024 x 1 CMOS RAM
Datasheet HM-6508883 DatasheetHM-6508883 Datasheet (PDF)

HM-6508/883 March 1997 1024 x 1 CMOS RAM Description The HM-6508/883 is a 1024 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On chip latches are provided for address allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The HM-6508/883 is a fully static RAM and .

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HM-6508/883 March 1997 1024 x 1 CMOS RAM Description The HM-6508/883 is a 1024 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On chip latches are provided for address allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The HM-6508/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature. Features • This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW Max • Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max • Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max • Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . .2.0V Min • TTL Compatible Input/Output • High Output Drive - 2 TTL Loads • On-Chip Address Register Ordering Information PACKAGE CERDIP TEMP. RANGE 180ns 250ns PKG. NO. F16.3 -55oC to +125oC HM1HM16508B/883 6508/883 Pinout HM1-6508/883 (CERDIP) TOP VIEW E 1 A0 2 A1 3 A2 4 A3 5 A4 6 Q 7 GND 8 16 VCC 15 D 14 W 13 A9 12 A8 11 A7 10 A6 9 A5 PIN A E W D Q DESCRIPTION Address Input Chip Enable Write Enable Data Input Data Output CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 2985.1 6-69 HM-6508/883 Functional Diagram A5 A6 A7 A8 A9 A LATCHED ADDRESS REGISTER 5 A 5 32 D A GATED COLUMN DECODER AND DATA I/O 5 A A 5 Q GATED ROW DECODER 32 32 x 32 MATRIX A W E LATCHED ADDRESS REGISTER A0 A1 A2 A3 A4 NOTES: 1. All lines positive logic - active high. 2. Three-state buffers: A high → output active. 3. Address latches and gated decoders: Latch on falling edge of E and gate on falling edge of E. 6-70 HM-6508/883 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V Typical Derating Factor . . . . . . . . . . .1.5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance (Typical, Note 1) θJA θJC CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . .VCC -2.0V to VCC Input Rise and Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max. Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1925 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. HM-6508/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER Output Low Voltage SYMBOL VOL (NOTE 1) CONDITIONS VCC = 4.5V, IOL = 3.2mA VCC = 4.5V, IOH = -0.4mA VCC = 5.5V, VI = GND or VCC VCC = 5.5V, VO = GND or VCC VCC = 2.0V, E = VCC, IO = 0mA, VI = VCC or GND GROUP A SUBGROUPS 1, 2, 3 TEMPERATURE -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC ICCOP VCC = 5.5V, (Note 2), E = 1MHz, IO = 0mA, VCC = 5.0V, IO = 0mA, VI = VCC or GND 1, 2, 3 -55oC ≤ TA ≤ +125oC 5 10 4 µA µA mA MIN MAX 0.4 UNITS V Output High Voltage VOH 1, 2, 3 2.4 - V Input Leakage Current II 1, 2, 3 -1.0 +1.0 µA µA Output Leakage Current IOZ 1, 2, 3 -1.0 +1.0 Data Retention Supply Current HM-6508B/883 HM-6508/883 Operating Supply Current ICCDR 1, 2, 3 Standby Supply Current ICCSB 1, 2, 3 -55oC ≤ TA ≤ +125oC - 10 µA NOTES: 1. All voltages referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP. 6-71 HM-6508/883 TABLE 2. HM-6508/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS (NOTES 1, 2) CONDITIONS VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V, Note 3 VCC = 4.5 and 5.5V VCC = 4.5.


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