HYB3166165AT-40

4M x 16-Bit Dynamic RAM (8k, 4k & 2k Refresh, EDO-Version) Advanced Information HYB 3164165AT(L) -40/-50/-60 HYB 3165165AT(L) -40/-50/-60 HYB 3166165AT(L) -40/-50/-60 4 194 304 words by 16-bit organization 0 to 70 °C operating temperature Hyper Page Mode - EDO - operation Performance: -40 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/write cycle time Hyper page mode (EDO) cycle time 40 10 20 69 16 -50 50 13 25 84 20 -60 60 15 30 104 25 ns ns ns ns ns Single + 3.3 V (± 0.3V) power supply Low power dissipation: -40 HYB3166165AT(L) HYB3165165AT(L) HYB3164165AT(L) 1008 756 612 -50 612 504 324 -60 450 360 324 mW mW mW 7.2 mW standby (TTL) 3.24 mW standby (MOS) 720 µA standby for L-version Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and Self Refresh (L-version only 2 CAS / 1 WE byte control 8192 refresh cycles/128 ms , 13 R/ 9C addresses (HYB 3164165AT) 4096 refresh cycles/ 64 ms , 12 R/ 10C addresses (HYB 3165165AT) 2048 refresh cycles/ 32 ms , 11 R/ 11C addresses (HYB 3166165AT) 256ms refresh period for L-versions Plastic Package: P-TSOPII-50 400 mil Semiconductor Group 1 6.97 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM This device is a 64 MBit dynamic RAM organized 4 194 304 x 16 bits. The device is fabricated on an advanced first generation 64Mbit 0,35 µm CMOS silicon gate process technology. The circuit and process design allow this device to achie...