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HYB3165800T-60 Dataheets PDF



Part Number HYB3165800T-60
Manufacturers Siemens Semiconductor Group
Logo Siemens Semiconductor Group
Description 8M x 8-Bit Dynamic RAM
Datasheet HYB3165800T-60 DatasheetHYB3165800T-60 Datasheet (PDF)

8M x 8-Bit Dynamic RAM (4k & 8k Refresh) HYB 3164800J/T -50/-60 HYB 3165800J/T -50/-60 Preliminary Information • • • • • • • • • • • 8 388 608 words by 8-bit organization 0 to 70 ˚C operating temperature Fast access and cycle time RAS access time: 50 ns (-50 version) 60 ns (-60 version) Cycle time: 90 ns (-50 version) 110 ns (-60 version) CAS access time: 13 ns ( -50 version) 15 ns ( -60 version) Fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) Single + 3.3 V (± 0.3V) powe.

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8M x 8-Bit Dynamic RAM (4k & 8k Refresh) HYB 3164800J/T -50/-60 HYB 3165800J/T -50/-60 Preliminary Information • • • • • • • • • • • 8 388 608 words by 8-bit organization 0 to 70 ˚C operating temperature Fast access and cycle time RAS access time: 50 ns (-50 version) 60 ns (-60 version) Cycle time: 90 ns (-50 version) 110 ns (-60 version) CAS access time: 13 ns ( -50 version) 15 ns ( -60 version) Fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) Single + 3.3 V (± 0.3V) power supply Low power dissipation max. 396 active mW ( HYB 3164800J/T-50) max. 360 active mW ( HYB 3164800J/T-60) max. 504 active mW ( HYB 3165800J/T-50) max. 432 active mW ( HYB 3165800J/T-60) 7.2 mW standby (TTL) 720 W standby (MOS) Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and self refresh modes Fast page mode capability 8192 refresh cycles/128 ms , 13 R/ 10C addresses (HYB 3164800J/T) 4096 refresh cycles/ 64 ms , 12 R/ 11C addresses (HYB 3165800J/T) Plastic Package: P-SOJ-34-1 500 mil HYB 3164(5)800J P-TSOPII-34-1 500 mil HYB 3164(5)800T Semiconductor Group 121 HYB 3164(5)800J/T-50/-60 8M x 8-DRAM This device is a 64 MBit dynamic RAM organized 8 388 608 by 8 bits. The device is fabricated in SIEMENS/IBM’s most advanced first generation 64Mbit CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. This DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)800J/T to be packaged in a 500 mil wide SOJ-34 or TSOP-34 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. Ordering Information Type HYB 3164800J-50 HYB 3164800J-60 HYB 3164800T-50 HYB 3164800T-60 HYB 3165800J-50 HYB 3165800J-60 HYB 3165800T-50 HYB 3165800T-60 Pin Names A0-A12 A0-A11 RAS OE I/O1-I/O8 CAS WRITE Vcc Vss Address Inputs for HYB 3164800J/T Address Inputs for HYB 3165800J/T Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply ( + 3.3V) Ground Ordering Code on request on request on request on request on request on request on request on request Package P-SOJ-34-1 P-SOJ-34-1 P-TSOPII-34-1 P-TSOPII-34-1 P-SOJ-34-1 P-SOJ-34-1 P-TSOPII-34-1 P-TSOPII-34-1 Descriptions 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns) 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns) 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns) 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns) Semiconductor Group 122 HYB 3164(5)800J/T-50/-60 8M x 8-DRAM P-SOJ-34-1 (500 mil) P-TSOPII-34-1 (500 mil) Pin Configuration Semiconductor Group 123 HYB 3164(5)800J/T-50/-60 8M x 8-DRAM TRUTH TABLE FUNCTION Standby Read Early-Write Delayed-Write Read-Modify-Write Fast Page Mode Read 1st.



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