HYB314100BJBJL-50-

4M x 1-Bit Dynamic RAM Low Power 4M x 1-Bit Dynamic RAM HYB 314100BJ/BJL -50/-60/-70 Advanced Information 4 194 304 words by 1-bit organization 0 to 70 ˚C operating temperature Fast Page Mode Operation Performance: -50 -60 60 15 30 110 40 -70 70 20 35 130 45 ns ns ns ns ns tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 95 35 Single + 3.3 V (± 0.3 V ) supply with a built-in Vbb generator Low power dissipation max. 252 mW active (-50 version) max. 216 mW active (-60 version) max. 198 mW active (-70 version) Standby power dissipation: 7.2 mW max. standby (TTL) 3.6 mW max. standby (CMOS) 720 µW max. standby (CMOS) for Low Power Version Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode capability All inputs and outputs TTL-compatible 1024 refresh cycles / 16 ms 1024 refresh cycles / 128 ms Low Power Version Plastic Packages: P-SOJ-26/20-5 with 300 mil width Semiconductor Group 1 4.96 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM The HYB 314100BJ/BJL is the new generation dynamic RAM organized as 4 194 304 words by 1-bit. The HYB 314100BJ/BJL utilizes CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514100B...