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HYB3118160BST-50 Dataheets PDF



Part Number HYB3118160BST-50
Manufacturers Siemens Semiconductor Group
Logo Siemens Semiconductor Group
Description 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
Datasheet HYB3118160BST-50 DatasheetHYB3118160BST-50 Datasheet (PDF)

1M x 16-Bit Dynamic RAM (1k & 4k -Refresh) HYB3116160BSJ/BST(L)-50/-60/-70 HYB3118160BSJ/BST(L)-50/-60/-70 Advanced Information • • • 1 048 576 words by 16-bit organization 0 to 70 °C operating temperature Performance: -50 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 90 35 -60 60 15 30 110 40 -70 70 20 35 130 45 ns ns ns ns ns • • • • • • • • • • Single + 3.3 V (± 0.3 V) supply Low power dissipation .

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1M x 16-Bit Dynamic RAM (1k & 4k -Refresh) HYB3116160BSJ/BST(L)-50/-60/-70 HYB3118160BSJ/BST(L)-50/-60/-70 Advanced Information • • • 1 048 576 words by 16-bit organization 0 to 70 °C operating temperature Performance: -50 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 90 35 -60 60 15 30 110 40 -70 70 20 35 130 45 ns ns ns ns ns • • • • • • • • • • Single + 3.3 V (± 0.3 V) supply Low power dissipation max. 720 active mW ( HYB3118160BSJ/BST-50) max. 648 active mW ( HYB3118160BSJ/BST-60) max. 576 active mW ( HYB3118160BSJ/BST-70) max. 360 active mW ( HYB3116160BSJ/BST-50) max. 324 active mW ( HYB3116160BSJ/BST-60) max. 288 active mW ( HYB3116160BSJ/BST-70) 7.2 mW standby (LV-TTL) 3.6 mW standby (LV-CMOS) 720 µW standby for L-version Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, self refresh Fast page mode capability 2 CAS / 1 WE All inputs, outputs and clocks fully LV-TTL-compatible 1024 refresh cycles / 16 ms for HYB 3118160BSJ 4096 refresh cycles / 64 ms for HYB 3116160BSJ Plastic Package: P-SOJ-42-1 400 mil P-TSOPII-50/44-1 400mil Semiconductor Group 1 1.96 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM The HYB 3116(8)160BSJ/BST is a 16 MBit dynamic RAM organized as 1 048 576 words by 16 bits. The HYB 3116(8)160BSJ/BST utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 3116(8)160BSJ/BST to be packaged in standard SOJ-42 and TSOPII-50/44 plastic package with 400mil width. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 3.3 V (± 0.3 V) power supply, direct interfacing with highperformance logic device families.The HYB3116160BSTL parts have a very low power „sleep mode“ suppported by Self Refresh. Ordering Information Type HYB 3116160BSJ-50 HYB 3116160BSJ-60 HYB 3116160BSJ-70 HYB 3118160BSJ-50 HYB 3118160BSJ-60 HYB 3118160BSJ-70 HYB 3116160BST-50 HYB 3116160BST-60 HYB 3116160BST-70 HYB 3118160BST-50 HYB 3118160BST-60 HYB 3118160BST-70 Ordering Code on request on request on request on request on request on request on request on request on request on request on request on request Package P-SOJ-42 400 mil P-SOJ-42 400 mil P-SOJ-42 400 mil P-SOJ-42 400 mil P-SOJ-42 400 mil P-SOJ-42 400 mil P-TSOPII-50/44 400 mil P-TSOPII-50/44 400 mil P-TSOPII-50/44 400 mil P-TSOPII-50/44 400 mil P-TSOPII-50/44 400 mil P-TSOPII-50/44 400 mil Descriptions DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) Pin Names A0 to A9 A0 to A9 A0 to A11 A0 to A7 RAS OE I/O1-I/O16 UCAS LCAS WE VCC VSS N.C. Row Address Inputs for 1k-refresh version HYB3118160BSJ/BST Column Addess Inputs for 1k-refresh version HYB3118160BSJ/BST Row Address Inputs for 4k-refresh version HYB3116160BSJ/BST Column Address Inputs for 4k-refresh version HYB3116160BSJ/BST Row Address Strobe Output Enable Data Input/Output Upper Column Address Strobe Lower Column Address Strobe Read/Write Input Power Supply (+ 3.3 V) Ground (0 V) not connected Semiconductor Group 2 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM P-SOJ-42 (400 mil) Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 N.C. N.C. WE RAS A11/NC A10/NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Vss I/O1 I/O16 I/O2 I/O3 I/O15 I/O4 I/O14 Vcc I/O13 I/O5 Vss I/O6 I/O12 I/O7 I/O11 I/O8 I/O10 N.C. I/O9 N.C. LCAS N.C. UCAS N.C. OE WE A9 RAS A11/N.C. A8 A10.N.C. A7 A0 A6 A1 A5 A2 A4 A3 Vss Vcc Vcc P-TSOPII-50/44 (400mil) 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 N.C. 15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26 N.C. LCAS UCAS OE A9 A8 A7 A6 A5 A4 Vss *) A11 and A10 are not connected for HYB3118160BSJ/BST (1k-refresh version) Truth Table RAS H L L L L L L L L LCAS H H L H L L H L L UCAS H H H L L H L L L WE H H H H H L L L H OE H H L L L H H H H I/O1-I/O8 High-Z High-Z Dout High-Z Dout Din Don't care Din High-Z 3 I/O9-I/O16 High-Z High-Z High-Z Dout Dout Don't care Din Din High-Z Operation Standby Refresh Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write NOP Semiconductor Group HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM I/O1 I/O2 I/O16 WE UCAS LCAS . . & Data in Buffer No. 2 Clock Generator 16 Data out Buffer 16 OE 8 A0 A1 A2 A.


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