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HYB3116400BJ-50 Dataheets PDF



Part Number HYB3116400BJ-50
Manufacturers Siemens Semiconductor Group
Logo Siemens Semiconductor Group
Description 4M x 4-Bit Dynamic RAM 2k & 4k Refresh
Datasheet HYB3116400BJ-50 DatasheetHYB3116400BJ-50 Datasheet (PDF)

3.3V 4M x 4-Bit Dynamic RAM HYB3116400BJ/BT(L) -50/-60/-70 HYB3117400BJ/BT(L) -50/-60/-70 Advanced Information • • • 4 194 304 words by 4-bit organization 0 to 70 °C operating temperature Performance: -50 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 90 35 -60 60 15 30 110 40 -70 70 20 35 130 45 ns ns ns ns ns • • • • • • • • Single + 3.3 V (± 0.3V ) supply Low power dissipation max. 396 active mW (HY.

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3.3V 4M x 4-Bit Dynamic RAM HYB3116400BJ/BT(L) -50/-60/-70 HYB3117400BJ/BT(L) -50/-60/-70 Advanced Information • • • 4 194 304 words by 4-bit organization 0 to 70 °C operating temperature Performance: -50 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 90 35 -60 60 15 30 110 40 -70 70 20 35 130 45 ns ns ns ns ns • • • • • • • • Single + 3.3 V (± 0.3V ) supply Low power dissipation max. 396 active mW (HYB3117400BJ/BT-50) max. 363 active mW (HYB3117400BJ/BT-60) max. 330 active mW (HYB3117400BJ/BT-70) max. 360 active mW (HYB3116400BJ/BT-50) max. 324 active mW (HYB3116400BJ/BT-60) max. 288 active mW (HYB3116400BJ/BT-70) 7.2 mW standby (LV-TTL) 3.6 mW standby (LV-CMOS) 720 µW standby for L-version Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, Self Refresh and test mode Fast page mode capability All inputs, outputs and clocks fully TTL-compatible 2048 refresh cycles / 32 ms for HYB3117400 4096 refresh cycles / 64 ms for HYB3116400 Plastic Package: P-SOJ-26/24-1 (300 mil) P-TSOPII-26/24-1 (300mil) Semiconductor Group 1 1.96 HYB 3116(7)400BJ/BT(L) -50/-60/-70 3.3V 4Mx4-DRAM The HYB 3116(7)400BJ/BT is a 16MBit dynamic RAM organized as 4194304 words by 4-bits. The HYB 3116(7)400BJ/BT utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 3116(7)400BJ/BT to be packaged in a standard SOJ 26/24 300 mil or TSOPII-26/24 300 mil wide plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 3.3 V (± 0.3 V) power supply, direct interfacing with high-performance logic device families.The HYB3116400BTL parts have a very low power „sleep mode“ supported by Self Refresh. Ordering Information Type HYB 3117400BJ-50 HYB 3117400BJ-60 HYB 3117400BJ-70 HYB 3117400BT-50 HYB 3117400BT-60 HYB 3117400BT-70 HYB 3116400BJ-50 HYB 3116400BJ-60 HYB 3116400BJ-70 HYB 3116400BT-50 HYB 3116400BT-60 HYB 3116400BT-70 HYB 3116400BTL-50 HYB 3116400BTL-60 HYB 3116400BTL-70 Ordering Code Package P-SOJ-26/24-1 300 mil P-SOJ-26/24-1 300 mil P-SOJ-26/24-1 300 mil P-TSOPII-26/24-1 300 mil P-TSOPII-26/24-1 300 mil P-TSOPII-26/24-1 300 mil P-SOJ-26/24-1 300 mil P-SOJ-26/24-1 300 mil P-SOJ-26/24-1 300 mil P-TSOPII-26/24-1 300 mil P-TSOPII-26/24-1 300 mil P-TSOPII-26/24-1 300 mil P-TSOPII-26/24-1 300 mil P-TSOPII-26/24-1 300 mil P-TSOPII-26/24-1 300 mil Descriptions DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) LP-DRAM (access time 50 ns) LP-DRAM (access time 60 ns) LP-DRAM (access time 70 ns) Semiconductor Group 2 HYB 3116(7)400BJ/BT(L) -50/-60/-70 3.3V 4Mx4-DRAM Vcc I/O1 I/O2 WE RAS N.C. A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 Vss I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 Vss Vcc I/O1 I/O2 WE RAS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 Vss I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 Vss HYB3117400BJ/BT HYB3116400BJ/BT P-SOJ-26/24-1 (300mil) P-TSOPII-26/24-1 (300mil) Pin Configuration Pin Names A0 to A10 A0 to A11 A0 to A9 RAS OE I/O1 -I/O4 CAS WE Row & Column Address Inputs for HYB3117400 Row Address Inputs for HYB3116400 Column Address Inputs for HYB3116400 Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply (+ 3.3 V) Ground (0 V) not connected VCC VSS N.C. Semiconductor Group 3 HYB 3116(7)400BJ/BT(L) -50/-60/-70 3.3V 4Mx4-DRAM I/O1 I/O2 I/O3 I/O4 WE CAS . & Data in Buffer No. 2 Clock Generator Data out Buffer 4 OE 4 11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 11 Column Address Buffer(11) 11 Column Decoder Refresh Controller Sense Amplifier I/O Gating 4 Refresh Counter (11) 11 Row 2048 x4 Address Buffers(11) 11 Decoder 2048 Row Memory Array 2048x2048x4 RAS No. 1 Clock Generator Block Diagram for HYB3117400 Semiconductor Group 4 HYB 3116(7)400BJ/BT(L) -50/-60/-70 3.3V 4Mx4-DRAM I/O1 I/O2 I/O3 I/O4 WE CAS . & Data in Buffer No. 2 Clock Generator Data out Buffer 4 OE 4 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 12 Column Address Buffer(10) 10 Column Decoder Refresh Controller Sense Amplifier I/O Gating 4 Refresh Counter (12) 12 Row 1024 x4 Address Buffers(12) 12 Decoder 4096 Row Memory Array 4096x1024x4 RAS No. 1 Clock Generator Block Diagram for HYB3116400 Semiconductor Group 5 HYB 3116(7)400BJ/BT(L) -50/-60/-70 3.3V 4Mx4-.


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