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ADC10040 Dataheets PDF



Part Number ADC10040
Manufacturers National Semiconductor
Logo National Semiconductor
Description 10-Bit/ 40 MSPS/ 3V/ 55.5 mW A/D Converter
Datasheet ADC10040 DatasheetADC10040 Datasheet (PDF)

ADC10040 10-Bit 40 MSPS 3V, 55 mW A/D Converter November 2004 ADC10040 10-Bit, 40 MSPS, 3V, 55.5 mW A/D Converter General Description The ADC10040 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power cons.

  ADC10040   ADC10040


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ADC10040 10-Bit 40 MSPS 3V, 55 mW A/D Converter November 2004 ADC10040 10-Bit, 40 MSPS, 3V, 55.5 mW A/D Converter General Description The ADC10040 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance. A unique sample-and-hold stage yields a fullpower bandwidth of 400 MHz. Operating on a single 3.0V power supply, this device consumes just 55.5 mW at 40 MSPS, including the reference current. The Standby feature reduces power consumption to just 13.5 mW. The differential inputs provide a full scale selectable input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. An internal +1.2V precision bandgap reference is used to set the ADC full-scale range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy. The output data format is 10-bit offset binary, or two’s complement. This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40˚C to +85˚C. Features n Single +3.0V operation n Selectable 2.0 VP-P, 1.5 VP-P, or 1.0 VP-P full-scale input swing n 400 MHz −3 dB input bandwidth n Low power consumption n Standby mode n On-chip reference and sample-and-hold amplifier n Offset binary or two’s complement data format n Separate adjustable output driver supply to accommodate 2.5V and 3.3V logic families n 28-pin TSSOP package Key Specifications n n n n n n n n n Resolution Conversion Rate Full Power Bandwidth DNL SNR (fIN = 11 MHz) SFDR (fIN = 11 MHz) Data Latency Supply Voltage Power Consumption, 40 MHz 10 Bits 40 MSPS 400 MHz ± 0.3 LSB (typ) 59.6 dB (typ) −80 dB (typ) 6 Clock Cycles +3.0V 55.5 mW Applications n n n n n n n n Ultrasound and Imaging Instrumentation Cellular Based Stations/Communications Receivers Sonar/Radar xDSL Wireless Local Loops Data Acquisition Systems DSP Front Ends Connection Diagram 20077801 © 2004 National Semiconductor Corporation DS200778 www.national.com ADC10040 Ordering Information Industrial (−40˚C ≤ TA ≤ +85˚C) ADC10040CIMT ADC10040CIMTX NS Package 28 Pin TSSOP 28 Pin TSSOP Tape & Reel Block Diagram 20077802 www.national.com 2 ADC10040 Pin Descriptions and Equivalent Circuits Pin No. ANALOG I/O Inverting analog input signal. With a 1.2V reference the full-scale input signal level is 1.0 VP-P. This pin may be tied to VCOM (pin 4) for single-ended operation. Symbol Equivalent Circuit Description 12 VIN− 13 VIN+ Non-inverting analog input signal. With a 1.2V reference the full-scale input signal level is 1.0 VP-P. 6 VREF Reference input. This pin should be bypassed to VSSA with a 0.1 µF monolithic capacitor. VREF is 1.20V nominal. This pin may be driven by a 1.20V external reference if desired. Do not load this pin. 7 VREFT 4 VCOM VREFT and VREFB are high impedance reference bypass pins only. Connect a 0.1 µF capacitor from each of these pins to VSSA. These pins should not be loaded. VCOM should also be bypassed with a 0.1 µF capacitor to VSSA. VCOM may be used to set the input common voltage VCM. 8 VREFB DIGITAL I/O 1 CLK Digital clock input. The range of frequencies for this input is 20 MHz to 40 MHz. The input is sampled on the rising edge of this input. DF = “1” Two’s Complement DF = “0” Offset Binary This is the standby pin. When high, this pin sets the converter into standby mode. When this pin is low, the converter is in active mode. IRS = “VDDA” 2.0 VP-P input range IRS = “VSSA” 1.5 VP-P input range IRS = “Floating” 1.0 VP-P input range If using both VIN+ and VIN- pins, (or differential mode), then the peak-to-peak voltage refers to the differential voltage (VIN+ - VIN-). 15 DF 28 STBY 5 IRS (Input Range Select) 3 www.national.com ADC10040 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit (Continued) Description 16–20, 23–27 D0–D9 Digital output data. D0 is the LSB and D9 is the MSB of the binary output word. ANALOG POWER Positive analog supply pins. These pins should be connected to a quiet 3,0V source and bypassed to analog ground with a 0.1 µF monolithic capacitor located within 1 cm of these pins. A 4.7 µF capacitor should also be used in parallel. Ground return for the analog supply. Positive digital supply pins for the ADC10040’s output drivers. This pin should be bypassed to digital ground with a 0.1 µF monolithic capacitor located within 1 cm of this pin. A 4.7 µF capacitor should also be used in parallel. The voltage on this pin should never exceed the voltage on VDDA by more than 300 mV. The ground return for the digital supply f.


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