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ADC10030 Dataheets PDF



Part Number ADC10030
Manufacturers National Semiconductor
Logo National Semiconductor
Description 10-Bit/ 30 MSPS/ 125 mW A/D Converter
Datasheet ADC10030 DatasheetADC10030 Datasheet (PDF)

ADC10030 10-Bit, 30 MSPS, 125 mW A/D Converter with Internal Sample and Hold January 2000 ADC10030 10-Bit, 30 MSPS, 125 mW A/D Converter with Internal Sample and Hold General Description The ADC10030 is a low power, high performance CMOS analog-to-digital converter that digitizes signals to 10 bits resolution at sampling rates up to 30 Msps while consuming a typical 125 mW from a single 5V supply. Reference force and sense pins allow the user to connect an external reference buffer amplifier t.

  ADC10030   ADC10030



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ADC10030 10-Bit, 30 MSPS, 125 mW A/D Converter with Internal Sample and Hold January 2000 ADC10030 10-Bit, 30 MSPS, 125 mW A/D Converter with Internal Sample and Hold General Description The ADC10030 is a low power, high performance CMOS analog-to-digital converter that digitizes signals to 10 bits resolution at sampling rates up to 30 Msps while consuming a typical 125 mW from a single 5V supply. Reference force and sense pins allow the user to connect an external reference buffer amplifier to ensure optimal accuracy. No missing codes is guaranteed over the full operating temperature range. The unique two-stage architecture achieves 9.1 Effective Bits with a 15 MHz input signal and a 30 MHz clock frequency. Output formatting is straight binary coding. To ease interfacing to 3V systems, the digital I/O power pins of the ADC10030 can be tied to a 3V power source, making the outputs 3V compatible. When not converting, power consumption can be reduced by pulling the PD (Power Down) pin high, placing the converter into a low power standby state, where it typically consumes less than 4 mW. The ADC10030’s speed, resolution and single supply operation makes it well suited for a variety of applications in video, imaging, communications, multimedia and high speed data acquisition. Low power, single supply operation ideally suit the ADC10030 for high speed portable applications, and its speed and resolution are ideal for charge coupled device (CCD) input systems. The ADC10030 comes in a space saving 32-pin TQFP and operates over the industrial (−40˚C ≤ TA ≤ +85˚C) temperature range. Features n n n n n n Internal Sample-and-Hold Single +5V Operation Low Power Standby Mode Guaranteed No Missing Codes TRI-STATE ® Outputs TTL/CMOS or 3V Logic Input/Output Compatible Key Specifications n Resolution n Conversion Rate n ENOB @ 15 MHz Input n DNL n Conversion Latency n PSRR n Power Consumption n Low Power Standby Mode 10 Bits 30 Msps 9.1 Bits (typ) 0.40 LSB (typ) 2 Clock Cycles 56 dB 125 mW (typ) < 3.5 mW (typ) Applications n n n n n n n Digital Video Communications Document Scanners Medical Imaging Electro-Optics Plain Paper Copiers CCD Imaging Connection Diagram DS101064-1 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2000 National Semiconductor Corporation DS101064 www.national.com ADC10030 Ordering Information Commercial Temperature Range (−40˚C ≤ TA ≤ +85˚C) ADC10030CIVT NS Package TQFP Block Diagram DS101064-2 www.national.com 2 ADC10030 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description 30 VIN Analog Input signal to be converted. Conversion range is VREF+ S to VREF− S. 31 VREF+ F VREF+ S VREF− F VREF− S Analog input that goes to the high side of the reference ladder of the ADC. This voltage should force VREF+ S to be in the range of 2.6V to 3.8V. Analog output used to sense the voltage at the top of the ADC reference ladder. Analog input that goes to the low side of the reference ladder of the ADC. This voltage should force VREF− S to be in the range of 1.7V to 2.8V. Analog output used to sense the voltage at the bottom of the ADC reference ladder. 32 2 1 9 CLK Converter digital clock input. VIN is sampled on the falling edge of CLK input. 8 PD Power Down input. When this pin is high, the converter is in the Power Down mode and the data output pins are in a high impedance state. Output Enable pin. When this pin and the PD pin are low, the output data pins are active. When this pin or the PD pin is high, the data output pins are in a high impedance state. 26 OE 14 thru 19 and 22 thru 25 D0–D9 Digital Output pins providing the 10-bit conversion results. D0 is the LSB, D9 is the MSB. Data is acquired on the falling edge of the CLK input and valid data is present 2.0 clock cycles plus tOD later. 3, 7, 28 VA Positive analog supply pins. These pins should be connected to a clean, quiet voltage source of +5V. VA and VD should have a common supply and be separately bypassed with 10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors. Positive digital supply pins. These pins should be connected to a clean, quiet voltage source of +5V. VA and VD should have a common supply and be separately bypassed with 10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors. 5, 10 VD 3 www.national.com ADC10030 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit (Continued) Description Positive supply pins for the digital output drivers. These pins should be connected to a clean, quiet voltage source of +3V to +5V and be separately bypassed with 10 µF to 50 µF capacitors. The ground return for the analog supply. AGND and DGND should be connected together close to the ADC10030 package. The ground return for the digital supply. AGND and DGND should be connected together close to the ADC10030 package. The ground return of the digital output drivers. 12, 21 VD I/O 4, 27, 29 AGND 6, 11 13, 20.


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