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ADC08062 Dataheets PDF



Part Number ADC08062
Manufacturers National Semiconductor
Logo National Semiconductor
Description A/D Converter
Datasheet ADC08062 DatasheetADC08062 Datasheet (PDF)

ADC08061/ADC08062 500 ns A/D Converter with S/H Function and Input Multiplexer June 1999 ADC08061/ADC08062 500 ns A/D Converter with S/H Function and Input Multiplexer General Description Using a patented multi-step A/D conversion technique, the 8-bit ADC08061 and ADC08062 CMOS ADCs offer 500 ns (typ) conversion time, internal sample-and-hold (S/H), and dissipate only 125 mW of power. The ADC08062 has a two-channel multiplexer. The ADC08061/2 family performs an 8-bit conversion using a 2-bit v.

  ADC08062   ADC08062


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ADC08061/ADC08062 500 ns A/D Converter with S/H Function and Input Multiplexer June 1999 ADC08061/ADC08062 500 ns A/D Converter with S/H Function and Input Multiplexer General Description Using a patented multi-step A/D conversion technique, the 8-bit ADC08061 and ADC08062 CMOS ADCs offer 500 ns (typ) conversion time, internal sample-and-hold (S/H), and dissipate only 125 mW of power. The ADC08062 has a two-channel multiplexer. The ADC08061/2 family performs an 8-bit conversion using a 2-bit voltage estimator that generates the 2 MSBs and two low-resolution (3-bit) flashes that generate the 6 LSBs. Input track-and-hold circuitry eliminates the need for an external sample-and-hold. The ADC08061/2 family performs accurate conversions of full-scale input signals that have a frequency range of DC to 300 kHz (full-power bandwidth) without need of an external S/H. The digital interface has been designed to ease connection to microprocessors and allows the parts to be I/O or memory mapped. Key Specifications n n n n n n Resolution Conversion Time Full Power Bandwidth Throughput rate Power Dissipation Total Unadjusted Error 8 bits 560 ns max (WR-RD Mode) 300 kHz 1.5 MHz 100 mW max ± 1⁄2 LSB and ± 1 LSB Features n n n n n 1 or 2 input channels No external clock required Analog input voltage range from GND to V+ Overflow output available for cascading (ADC08061) ADC08061 pin-compatible with the industry standard ADC0820 Applications n n n n Mobile telecommunications Hard disk drives Instrumentation High-speed data acquisition systems Block Diagram DS011086-1 * ADC08061 ** ADC08062 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS011086 www.national.com Connection Diagrams DS011086-15 DS011086-14 Dual-In-Line and Wide-Body Small-Outline Packages N20A or M20B Dual-In-Line and Wide-Body Small-Outline Packages N20A or M20B Ordering Information Industrial (−40˚C ≤ TA ≤ 85˚C) ADC08061BIN, ADC08062BIN ADC08061CIWM, ADC08062CIWM Package N20A M20B Pin Description These are analog inputs. The input range is GND–50 mV ≤ VINPUT ≤ V+ + 50 mV. The ADC08061 has a single input (VIN) and the ADC08062 has a two-channel multiplexer (VIN1–2). DB0–DB7 TRI-STATE data outputs — bit 0 (LSB) through bit 7 (MSB). WR /RDY WR-RD Mode (Logic high applied to MODE pin) WR: With CS low, the conversion is started on the falling edge of WR. The digital result will be strobed into the output latch at the end of conversion (see Figures 2, 3, 4). : RD Mode (Logic low applied to MODE pin) RDY: This is an open drain output (no internal pull-up device). RDY will go low after the falling edge of CS and return high at the end of conversion. MODE Mode: Mode (RD or WR-RD) selection input — This pin is pulled to a logic low through an internal 50 µA current sink when left unconnected. RD Mode is selected if the MODE pin is left unconnected or externally forced low. A complete conversion is accomplished by pulling RD low until output data appears. WR-RD Mode is selected when a high is applied to the MODE pin. A conversion starts with the WR signal’s rising edge and then using RD to access the data. WR-RD Mode (logic high on the MODE pin) This is the active low Read input. With a logic low applied to the CS pin, the TRI-STATE data outputs (DB0–DB7) will be activated when RD goes low (Figures 2, 3, 4). RD Mode (logic low on the MODE pin) VIN, VIN1–8 With CS low, a conversion starts on the falling edge of RD. Output data appears on DB0–DB7 at the end of conversion(see Figures 1, 5). This is an active low output that indicates that a conversion is complete and the data is in the output latch. INT is reset by the rising edge of RD. This is the power supply ground pin. The ground pin should be connected to a “clean” ground reference point. These are the reference voltage inputs. They may be placed at any voltage between GND − 50 mV and V+ + 50 mV, but VREF+ must be greater than VREF−. Ideally, an input voltage equal to VREF− produces an output code of 0, and an input voltage greater than VREF+ − 1.5 LSB produces an output code of 255. For the ADC08062, an input voltage on any unselected input that exceeds V+ by more than 100 mV or is below GND by more than 100 mV will create errors in a selected channel that is operating within proper operating conditions. This is the active low Chip Select input. A logic low signal applied to this input pin enables the RD and WR inputs. Internally, the CS signal is ORed with RD and WR signals. Overflow Output. If the analog input is higher than VREF+ − 1⁄2 LSB, OFL will be low at the end of conversion. It can be used when cascading two ADC08061s to achieve higher resolution (9 bits). This output is always active and does not go into TRI-STATE as DB0–DB7 do. When OFL is set, all data outputs remain high when the ADC08061’s output data is read. No connection. INT GND VREF−, VREF+ CS OFL RD NC www.national.com 2 Pin Description A0 (Conti.


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