Document
AT17 Series
Features
• E2 Programmable 65,536 x 1, 131,072 x 1, and 262,144 x 1 bit Serial Memories Designed
To Store Configuration Programs For Programmable Gate Arrays
• Simple Interface to SRAM FPGAs Requires Only One User I/O Pin • Compatible With AT6000 FPGAs, ATT3000 FPGA, EPF8000 FPGAs, ORCA FPGAs,
XC2000, XC3000, XC4000, XC5000 FPGAs, MPA1000
• Cascadable To Support Additional Configurations or Future Higher-density Arrays
(17C128 and 17C256 only)
• Low-power CMOS EEPROM Process • Programmable Reset Polarity • Available In the Space-efficient Plastic DIP or Surface-mount
PLCC and SOIC Packages • In-System Programmable Via 2-Wire Bus • Emulation of 24CXX Serial EPROMs • Available in 3.3V ± 10% LV Version
FPGA Configuration E2PROM
65K, 128K and 256K
Description
The AT17C65/128/256 and AT17LV65/128/256 (AT17 Series) FPGA Configuration EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17 Series is packaged in the 8-pin DIP and the popular 20-pin PLCC and SOIC. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17 Series organization supplies enough memory to configure one or multiple smaller FPGAs. Using a special feature of the AT17 Series, the user can select the polarity of the reset function by programming a special EEPROM bit. The AT17 Series can be programmed with industry standard programmers.
AT17C65 AT17C128 AT17C256
Pin Configurations
20-pin PLCC 20-Pin SOIC
8-Pin DIP
0391E-A–5/97
1
Controlling The AT17 Series Serial EEPROMs
Most connections between the FPGA device and the Serial EEPROM are simple and self-explanatory. • The DATA output of the AT17 Series drives DIN of the FPGA devices. • The master FPGA CCLK output drives the CLK input of the AT17 Series. • The CEO output of any AT17C/LV128/256 drives the CE input of the next AT17C/LV128/256 in a cascade chain of PROMs. • SER_EN must be connected to VCC. There are, however, two different ways to use the inputs CE and OE, as shown in the AC Characteristics waveforms. tion cycle. If a system reset is applied to the FPGA, it will abort the original configuration and then reset itself for a new configuration, as intended. Of course, the AT17 Series does not see the external reset signal and will not reset its internal address counters and, consequently, will remain out of sync with the FPGA for the remainder of the configuration cycle.
Condition 2
The FPGA D/P output drives only the CE input of the AT17 Series, while its OE input is driven by the inversion of the input to the FPGA RESET input pin. This connection works under all normal circumstances, even when the user aborts a configuration before D/P has gone High. A High level on the RESET/OE input to the AT17C/LVxxx – during FPGA reset – clears the Configurator's internal address pointer, so that the reconfiguration starts at the beginning. The AT17 Series does not require an inverter since the RESET polarity is programmable.
Condition 1
The simplest connection is to have the FPGA D/P output drive both CE and RESET/OE in parallel (Figure 1). Due to its simplicity, however, this method will fail if the FPGA receives an external reset condition during the configura-
Block Diagram
2
AT17 Series
AT17 Series
Pin Configurations
PLCC/ SOIC Pin 2 4 DIP Pin 1 2 Name DATA CLK I/O I/O I Description Three-state DATA output for reading. Input/Output pin for programming. Clock input. Used to increment the internal address and bit counter for reading and programming. RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and RESET/OE inputs enables the data output driver. A High level on RESET/OE resets both the addresss and bit counters. A logic polarity of this input is programmable as either RESET/OE or RESET/OE. This document describes the pin as RESET/OE. I Chip Enable input. Used for device selection. A Low level on both CE and OE enables the data output driver. A High level on CE disables both the address and bit counters and forces te device into a low power mode. Note this pin will not enable/disable the device in 2-wire Serial mode (ie; when SER_EN is Low). Ground Pin O Chip Enable Out output. This signal is asserted Low on the clock cycle following the last bit read from the memory. It will stay Low as long as CE and OE are both Low. It will then follow CE until OE goes High. Thereafter CEO will stay High until the entire PROM is read again and senses the status of RESET polarity. Device selection input, A2. This is used to enable (or select) the device during programming and when SER_EN is Low (see Programming Guide for more details). Serial enable is normally high during FPGA loading operations. Bringing SER_EN low, enables the 2-wire serial interface for programming. +3.3V/+5V power supply pin.
6
3
RESET/OE
8
4
CE
10 14
5 6
GND CEO
A2
I
17 20
7 8
SER_EN VCC
I
Absolute Maximum Ratings*
Operating Temperature........