ACS573MS

ACS573MS January 1996 Radiation Hardened Octal Three-State Transparent Latch Pinouts 20 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C TOP VIEW OE D0 D1 D2 D3 D4 D5 1 2 3 4 5 6 7 8 9 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 LE Features Devices QML Qualified in Accordance with MIL-PRF-38535 Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96724 and Intersil’s QM Plan 1.25 Micron Radiation Hardened SOS CMOS Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si) Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ) SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg Dose Rate Upset . . . . . . . . . . . . . . . . >10 Dose Rate Survivability . . . . . . . . . . . >10 Latch-Up Free Under Any Conditions Military Temperature Range . . . . . . . . . . . . . . . . . . -55 oC 11 12 RAD (Si)/s, 20ns Pulse RAD (Si)/s, 20ns Pulse to +125oC D6 D7 Significant Power Reduction Compared to ALSTTL Logic DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min Input Current ≤ 1µA at VOL, VOH Fast Propagation Delay . . . . . . . . . . . . . . . . 17ns (Max), 12ns (Typ) GND 10 20 LEAD CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C TOP VIEW Description OE 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 ...