Document
Class D/1-Bit Audio Power Output Stage AD1991
FEATURES Class D/1-Bit Audio Power Output Stage 5 V Analog and Digital Supply Voltages Power Stage Power Supply 8 V to 20 V Output Power @ 0.1% THD + N Stereo Mode 2 ؋ 20 W @ 4 ⍀ @ 14.4 V 2 ؋ 20 W @ 8 ⍀ @ 20 V Mono Mode 1 ؋ 40 W @ 4 ⍀ @ 20 V RON < 320 m⍀ (per Transistor) Efficiency > 85% @ Full Power/8 ⍀ Clickless Mute Function Turn-On and Turn-Off Pop Suppression Short-Circuit Protection Overtemperature Protection Data Loss Protection 2-Channel BTL Outputs or 4-Channel Single-Ended Outputs 52-Lead Exposed Pad TQFP Package Low Cost DMOS Process APPLICATIONS PC Audio Systems Minicomponents Automotive Amplifiers Home Theater Systems Televisions GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS 2-Channel Mode
AVDD DVDD PVDD 6 OUTA INA LEFT INPUT A1 A2 3
INB
B1 B2
LEVEL SHIFTER AND SWITCH CONTROL H-BRIDGE
OUTB 3 OUTC
INC RIGHT INPUT
C1 C2
3
IND
D1 OUTD D2 3 CURRENT OVERLOAD THERMAL SHUTDOWN THERMAL WARNING DATA LOSS 14 PGND
CLK RST/PDN MUTE
،n THERMAL PROTECTION SHORT-CIRCUIT PROTECTION MUTE CONTROL
4 AGND DGND
2 TEST CONTROL
4-Channel Mode
AVDD DVDD PVDD 6
The AD1991 is a 2-channel BTL or 4-channel single-ended class D audio power output stage. The part is configured during reset to be in either 2-channel mode or 4-channel mode. To protect the IC as well as the connected speakers, the AD1991 provides turn-on and turn-off pop suppression, short-circuit protection, and overtemperature shutdown. To control the IC, a power-down/reset input and a mute pin are available. The output stage can be operated over a power supply range from 8 V to 20 V. In 2-channel mode, Transistors A1, B2, C1, and D2 are turned on by a Logic 1 on inputs INA and INC, and Transistors A2, B1, C2, and D1 are turned on by a Logic 0 on inputs INA and INC. In 4-channel mode, Transistors A1, B1, C1, and D1 are turned on by a Logic 1 on the four inputs, and Transistors A2, B2, C2, and D2 are turned on by a Logic 0 on the four inputs (see the Functional Block Diagrams).
INA
A1 A2
OUTA 3
LOAD REQUIRING DC VOLTAGE SUPPLY
INB
B1 B2
LEVEL SHIFTER AND SWITCH CONTROL H-BRIDGE
OUTB 3
INC
C1 C2
OUTC 3
IND
D1 D2
OUTD 3
LOAD REQUIRING DC VOLTAGE SUPPLY
CLK RST/PDN MUTE
،n THERMAL PROTECTION SHORT-CIRCUIT PROTECTION MUTE CONTROL
CURRENT OVERLOAD THERMAL SHUTDOWN THERMAL WARNING DATA LOSS 14
REV. 0
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4 AGND DGND
2 TEST CONTROL
PGND
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(AV = 5 V, DV = 5 V, PV = 20 V, Ambient Temperature = 25؇C, Impedance = 8 ⍀, unless otherwise noted.) AD1991–SPECIFICATIONS1 Load
DD DD DDX
Parameter OUTPUT POWER PO (f = 1 kHz SINE WAVE) EFFICIENCY RON Per High-Side Transistor Per Low-Side Transistor Temperature Coefficient THERMAL WARNING ACTIVE THERMAL SHUTDOWN ACTIVE OVERCURRENT SHUTDOWN ACTIVE POWER SUPPLIES Supply Voltage AVDD Supply Voltage DVDD Supply Voltage PVDDX Power-Down Current AVDD DVDD PVDDX Operating Current AVDD DVDD PVDDX DIGITAL I/O Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Leakage Current on Digital Inputs
NOTES 1 Performance of both channels is identical. 2 Measurement requires PWM modulator. Specifications subject to change without notice.
2
Min
Typ 20 20 87 260 190 0.7 135 150 5 5.0 5.0 8 to 20 6 1 17 1.8 4 40
Max
Unit W W %
Test Conditions RL = 4 Ω, PVDDX = 14 V RL = 8 Ω, PVDDX = 20 V f = 1 kHz, PO = 20 W, RL = 8 Ω @1A @1A Die temperature Die temperature
320 235
3.8 4.5 4.5 6.5
6.75 5.5 5.5 22.5 14 13
mΩ mΩ mΩ/°C °C °C A V V V µA µA µA mA mA mA
RST/PDN held low RST/PDN held low RST/PDN held low
2.75 5.2
50:50 384 kHz square wave on INA and INC
2.0 DVDD – 0.8
DVDD 1.2 0.4 10
V V V V µA
@ 2 mA @ 2 mA
DIGITAL TIMING CHARACTERISTICS
Symbol tPDL tPST tNOL tPDRP tMSU tMH tMPDL Parameter
(Guaranteed over –40؇C to +85؇C, AVDD = DVDD = 5 V ؎ 10%, PVDDX = 20 V ؎ 10%, Edge Speed = Slowest, Nonoverlap Time = Shortest.)
Min Typ 3.5 25 to 40 20 5 5 3 Max 30 Unit ns ns ns ns ns ns s
Input transition to output initial response Power transistor switching time Nonoverlap time RST/PDN minimum low pulsewidth Mode pin setup time before RST/PDN going high Mode pin hold time after RST/PDN going high MUTE asserted to output initial response
Specifications subject to change without notice.
–2–
REV. 0
AD1991
INA
tPST tPST
tPST tPST
tNOL tPDL tPDL
tNOL
OUTA OUTB
Figure 1. Output Timing
RST/PDN
tPDRP
MODEx
tMSU
tMH
Figure 2. RESET and Mode Timing.