Document
Data Sheet
FEATURES
16-bit resolution AD5543 14-bit resolution AD5553 ±1 LSB DNL ±1 LSB INL Low noise: 12 nV/√Hz Low power: IDD = 10 µA 0.5 µs settling time 4-quadrant multiplying reference input 2 mA full-scale current ± 20%, with VREF = 10 V Built-in RFB facilitates voltage conversion 3-wire interface Ultracompact 8-lead MSOP and 8-lead SOIC packages
APPLICATIONS
Automatic test equipment Instrumentation Digitally controlled calibration Industrial control programmable logic controllers
GENERAL DESCRIPTION
The AD5543/AD5553 are precision 16-/14-bit, low power, current output, small form factor digital-to-analog converters (DACs). They are designed to operate from a single 5 V supply with a ±10 V multiplying reference.
The applied external reference, VREF, determines the full-scale output current. An internal feedback resistor (RFB) facilitates the R-2R and temperature tracking for voltage conversion when combined with an external operational amplifier.
A serial data interface offers high speed, 3-wire microcontrollercompatible inputs using serial data in (SDI), clock (CLK), and chip select (CS).
The AD5543/AD5553 are packaged in ultracompact (3 mm × 4.7 mm) 8-lead MSOP and 8-lead SOIC packages.
Rev. H
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Current Output/Serial Input, 16-/14-Bit DACs AD5543/AD5553
FUNCTIONAL BLOCK DIAGRAM
AD5543/AD5553
VDD
RFB
02917-001
VREF
DAC
CS
CLK SDI
CONTROL LOGIC
16 OR 14
DAC REGISTER
16 OR 14
16-BIT/14-BIT SHIFT REGISTER
Figure 1.
1.0 0.8 0.6 0.4 0.2
0 –0.2 –0.4 –0.6 –0.8 –1.0
IOUT GND
0 4096 8152 12,288 16,384 20,480 24,575 28,672 32,768 36,864 40,960 45,056 49,152 53,248 57,344 61,440 65,536
02917-002
CODE
Figure 2. Integral Nonlinearity (INL)
2
0
–2
–4
–6
–8
–10
–12
–14 10k
100k
1M
10M
FREQUENCY (Hz)
Figure 3. Reference Multiplying Bandwidth
100M
INL (LSB)
GAIN (dB)
02917-025
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AD5543/AD5553
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3
Timing Diagrams.......................................................................... 4 Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Circuit Operation ............................................................................. 9
DAC Section.................................................................................. 9 Serial Data Interface ....................................................................... 10
ESD Protection Circuits............................................................. 10 PCB Layout and Power Supply Bypassing .............................. 10
REVISION HISTORY
1/2020—Rev. G to Rev. H Changes to Equation 4 and Figure 22 .......................................... 11 Change to Table 8 ........................................................................... 13 Change to Evaluation Board Section ........................................... 14 Changes to Ordering Guide .......................................................... 20
12/2015—Rev. F to Rev. G Deleted Positive Output Voltage Section..................................... 11
1/2012—Rev. E to Rev. F Added Figure 15, Renumbered Sequentially ................................ 8 Change to Table 9 ........................................................................... 13 Changes to Figure 27...................................................................... 15 Changes to Figure 28...................................................................... 16 Replaced Figure 29, Figure 30, and Figure 31............