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32-Channel, 14-Bit Voltage-Output DAC
AD5532
FEATURES
High integration: 32-channel DAC in 12 mm × 12 mm CSPBGA
Adjustable voltage output range Guaranteed monotonic Readback capability DSP/microcontroller compatible serial interface Output impedance:
0.5 Ω (AD5532-1, AD5532-2) 500 Ω (AD5532-3) 1 kΩ (AD5532-5) Output voltage span: 10 V (AD5532-1, AD5532-3, AD5532-5) 20 V (AD5532-2) Infinite sample-and-hold capability to ±0.018% accuracy Temperature range −40°C to +85°C
APPLICATIONS
Automatic test equipment Optical networks Level setting Instrumentation Industrial control systems Data acquisition Low cost I/O
GENERAL DESCRIPTION
The AD55321 is a 32-channel, 14-bit voltage-output DAC with an additional infinite sample-and-hold mode. The selected DAC register is written to via the 3-wire serial interface; VOUT for this DAC is then updated to reflect the new contents of the DAC register. DAC selection is accomplished via Address Bits A0–A4. The output voltage range is determined by the offset voltage at the OFFS_IN pin and the gain of the output amplifier. It is restricted to a range from VSS + 2 V to VDD – 2 V because of the headroom of the output amplifier.
The device is operated with AVCC = 5 V ± 5%; DVCC = 2.7 V to 5.25 V; VSS = −4.75 V to −16.5 V; and VDD = 8 V to 16.5 V. The AD5532 requires a stable 3 V reference on REF_IN as well as an offset voltage on OFFS_IN.
PRODUCT HIGHLIGHTS
1. 32-channel, 14-bit DAC in one package, guaranteed monotonic.
2. Available in a 74-lead CSPBGA package with a body size of 12 mm ×12 mm.
3. Droopless/infinite sample-and-hold mode.
DVCC AVCC REF_IN REF_OUT OFFS_IN
VDD VSS
AD5532
VIN TRACK/RESET
BUSY DAC_GND
AGND DGND
SER/PAR
ADC
DAC
14-BIT BUS
MUX
DAC
MODE
DAC
INTERFACE CONTROL
LOGIC
ADDRESS INPUT REGISTER
SCLK DIN DOUT
SYNC/CS A4–A0 CAL OFFSET_SEL
Figure 1. Functional Block Diagram
VOUT0
VOUT31 OFFS_OUT WR
00939-C-001
Rev. D
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AD5532
TABLE OF CONTENTS
Specifications..................................................................................... 3
ISHA Mode.................................................................................... 5
Timing Characteristics..................................................................... 6
Parallel Interface ........................................................................... 6
Parallel Interface Timing Diagrams ........................................... 6
Serial Interface .............................................................................. 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Terminology .................................................................................... 11
Dac Mode .................................................................................... 11
ISHA Mode.................................................................................. 11
Typical Performance Characteristics ........................................... 12
Functional Description .................................................................. 14
REVISION HISTORY
6/10—Data Sheet Changed from Rev. C to Rev. D Changes to Table 5......................................................................8 Changes to Ordering Guide ....................................................20
6/04—Data Sheet Changed from Rev. B to Rev. C Updated Format........................................................... Universal Changed LFBGA to CSPBGA.................................... Universal Changes to Outline Dimensions.............................................24 Changes to Ordering Guide ....................................................24
6/02—Data Sheet Changed from Rev. A to Rev. B Term SHA changed to ISHA ........................................... Global Changes to Absolute Maximum Ratings .................................6 Changes to Ordering Guide ......................................................6 Changes to Functional Description .......................................11 Changes to Table 8....................................................................11 Changes to ISHA Mode .....................................