Document
PRELIMINARY TECHNICAL DATA
=
Preliminary Technical Data
FEATURES Fast Throughput Rate: 3Msps Wide Input Bandwidth: 50MHz No Pipeline Delays with SAR ADC Excellent DC Accuracy Performance Two Parallel Interface Modes Low Power: 90mW (Full-Power) and 5mW (NAP Mode) Standby Mode: 1µA max Single +5V Supply Operation Internal +2.5V Reference Full-Scale Overrange Mode (using 15th bit) System Offset Removal via User Access Offset Register Nominal 0 to +2.5V Input with Shifted Range Capability Pin Compatible Upgrade of 12-Bit AD7482 GENERAL DESCRIPTION
VREF3 BUF
3MSPS, 14-Bit SAR ADC AD7484
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND CBIAS DVDD DGND VREF1 VREF2 2.5 V REFERENCE
VIN
T/H
14-Bit Error Correcting SAR
AD7484
MODE1 MODE2 D14 D13 D12 D11 D10 D9 D8 D7
CLIP NAP STBY RESET CONVST VDRIVE
CONTROL LOGIC AND I/O REGISTERS
The AD7484 is a 14-bit, high speed, low power, successive-approximation ADC. The part features a parallel interface with throughput rates up to 3Msps. The part contains a low-noise, wide bandwidth track/hold amplifier which can handle input frequencies in excess of 50MHz. The conversion process is a proprietary algorithmic successive-approximation technique which results in no pipeline delays. The input signal is sampled and a conversion is initiated on the falling edge of the CONVST signal. The conversion process is controlled via an internally trimmed oscillator. Interfacing is via standard parallel signal lines making the part directly compatible with microcontrollers and DSPs. The AD7484 provides excellent ac and dc performance specifications. Factory trimming ensures high dc accuracy resulting in very low INL, offset and gain errors. The part uses advanced design techniques to achieve very low power dissipation at high throughput rates. Power consumption in normal mode of operation is 90mW. There are two power-saving modes: a NAP mode, which keeps the reference circuitry alive for a quick power up while consuming 5mW and a STANDBY mode which reduces power consumption to a mere 5µW.
WRITE
BUSY
RD
D0
D1
D2
D3
D4
D5
The AD7484 features an on-board +2.5V reference but the part can also accomodate an externally-provided +2.5V reference source. The nominal analog input range is 0 to +2.5V but an offset shift capability allows this nominal range to be offset by +/-200mV. This allows the user considerable flexibility in setting the bottom end reference point of the signal range, a useful feature when using single-supply op-amps. The AD7484 also provides the user with an 8% overrange capability via a 15th bit. Thus, if the analog input range strays outside the nominal by up to 8%, the user can still accurately resolve the signal by using the 15th bit. The AD7484 is powered from a +4.75V to +5.25V supply. The part also provides a VDRIVE pin which allows the user to set the voltage levels for the digital interface lines. The range for this VDRIVE pin is from +2.7V to +5.25V. The part is housed in a 48-pin LQFP package and is specified over a -40°C to +85°C temperature range.
REV. PrC 7/13/01
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
CS
D6
PRELIMINARY TECHNICAL DATA
AD7484–SPECIFICATIONS
Parameter DYNAMIC PERFORMANCE Signal to Noise + Distortion (SINAD)2 Signal to Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity 2 Differential Nonlinearity 2 Offset Error2 Gain Error 2 ANALOG INPUT Input Voltage DC Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT VREF Input Voltage VREF Input DC Leakage Current VREF Input Capacitance VREF Output Voltage VREF Error @ 25°C VREF Error TMIN to TMAX VREF Output Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN2 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance 2,3 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD VDRIVE IDD Normal Mode (Static) Normal Mode (Operational) NAP Mode Standby Mode 7/13/01 Specification 78 78 -90 TBD TBD TBD 10 10 50 TBD 14 TBD ±1 TBD ±1 ±1.5 ±1.5 -200 +2.7 TBD 10 +2.5 ±1 TBD +2.5 TBD TBD TBD TBD 0.4 TBD TBD
(TA = 25؇ C, VDD = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fSAMPLE = 3MSPS)
Units dB dB dB dB min min max max Test Conditions/Comm.