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AD73322 Dataheets PDF



Part Number AD73322
Manufacturers Analog Devices
Logo Analog Devices
Description Low Cost/ Low Power CMOS General-Purpose Dual Analog Front End
Datasheet AD73322 DatasheetAD73322 Datasheet (PDF)

a Low Cost, Low Power CMOS General-Purpose Dual Analog Front End AD73322 FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 DVDD FEATURES Two 16-Bit A/D Converters Two 16-Bit D/A Converters Programmable Input/Output Sample Rates 78 dB ADC SNR 77 dB DAC SNR 64 kS/s Maximum Sample Rate –90 dB Crosstalk Low Group Delay (25 ␮s Typ per ADC Channel, 50 ␮s Typ per DAC Channel) Programmable Input/Output Gain Flexible Serial Port which Allows Up to Four Dual Codecs to be Connected in Cascade Giving Eight I/O Channel.

  AD73322   AD73322


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a Low Cost, Low Power CMOS General-Purpose Dual Analog Front End AD73322 FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 DVDD FEATURES Two 16-Bit A/D Converters Two 16-Bit D/A Converters Programmable Input/Output Sample Rates 78 dB ADC SNR 77 dB DAC SNR 64 kS/s Maximum Sample Rate –90 dB Crosstalk Low Group Delay (25 ␮s Typ per ADC Channel, 50 ␮s Typ per DAC Channel) Programmable Input/Output Gain Flexible Serial Port which Allows Up to Four Dual Codecs to be Connected in Cascade Giving Eight I/O Channels Single (+2.7 V to +5.5 V) Supply Operation 73 mW Typ Power Consumption at 3.0 V On-Chip Reference 28-Lead SOIC and 44-Lead LQFP Packages APPLICATIONS General Purpose Analog I/O Speech Processing Cordless and Personal Communications Telephony Active Control of Sound and Vibration Data Communications Wireless Local Loop GENERAL DESCRIPTION AD73322 VFBP1 VINP1 VINN1 VFBN1 VOUTP1 VOUTN1 REFOUT REFCAP VFBP2 VINP2 VINN2 VFBN2 VOUTP2 VOUTN2 ADC CHANNEL 1 SDI SDIFS DAC CHANNEL 1 SPORT REFERENCE SCLK SE RESET ADC CHANNEL 2 MCLK SDOFS DAC CHANNEL 2 SDO AGND1 AGND2 DGND The AD73322 is a dual front-end processor for general-purpose applications including speech and telephony. It features two 16-bit A/D conversion channels and two 16-bit D/A conversion channels. Each channel provides 77␣ dB signal-to-noise ratio over a voiceband signal bandwidth. It also features an input-tooutput gain network in both the analog and digital domains. This is featured on both codecs and can be used for impedance matching or scaling when interfacing to Subscriber Line Interface Circuits (SLICs). The AD73322 is particularly suitable for a variety of applications in the speech and telephony area, including low bit rate, high quality compression, speech enhancement, recognition, and synthesis. The low group delay characteristic of the part makes it suitable for single or multichannel active control applications. The A/D and D/A conversion channels feature programmable input/output gains with ranges of 38 dB and 21 dB respectively. An on-chip reference voltage is included to allow single-supply operation. This reference is programmable to accommodate either 3 V or 5 V operation. The sampling rate of the codecs is programmable with four separate settings, offering 64 kHz, 32 kHz, 16 kHz and 8 kHz sampling rates (from a master clock of 16.384 MHz). A serial port (SPORT) allows easy interfacing of single or cascaded devices to industry standard DSP engines. The SPORT transfer rate is programmable to allow interfacing to both fast and slow DSP engines. The AD73322 is available in 28-lead SOIC and 44-lead LQFP packages. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD73322–SPECIFICATIONS1 16.384 MHz, f Parameter REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, VREFOUT Minimum Load Resistance Maximum Load Capacitance INPUT AMPLIFIER Offset Maximum Output Swing Feedback Resistance Feedback Capacitance ANALOG GAIN TAP Gain at Maximum Setting Gain at Minimum Setting Gain Resolution Gain Accuracy Settling Time Delay ADC SPECIFICATIONS Maximum Input Range at VIN2, 3 Nominal Reference Level at VIN (0 dBm0) Absolute Gain PGA = 0 dB PGA = 38 dB Gain Tracking Error Signal to (Noise + Distortion) PGA = 0 dB Min 1.08 1.2 50 130 1.2 (AVDD = +3 V ؎ 10%; DVDD = +3 V ؎ 10%; DGND = AGND = 0 V, fDMCLK = SAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted) Units Test Conditions/Comments 5VEN = 0 1.32 V ppm/°C 0.1 µF Capacitor Required from REFCAP to AGND2 Ω V Unloaded kΩ pF mV V Ω pF AD73322A Typ Max 1.08 1 1.32 100 ± 1.0 1.578 50 100 +1 –1 5 ± 1.0 1.0 0.5 1.578 –2.85 1.0954 –6.02 –0.5 –1.5 0.4 –0.7 ± 0.1 78 78 57 56 –84 –70 –65 –71 –100 –100 –70 +10 –65 25 20 +1 –1 16 25 100 –73 –60 +1.2 +0.1 Max Output Swing = (1.578/1.2) × VREFCAP fC = 32 kHz Bits % µs µs V p-p dBm V p-p dBm dB dB dB dB dB dB dB dB dB dB dBm0 dB dB dB mV dB µs kΩ Gain Step Size = 0.0625 Output Unloaded Tap Gain Change of –FS to +FS 5VEN = 0 Measured Differentially Max Input = (1.578/1.2) × VREFCAP Measured Differentially 72 55 52 PGA = 38 dB Total Harmonic Distortion PGA = 0 dB PGA = 38 dB Intermodulation Distortion Idle Channel Noise Crosstalk ADC-to-DAC ADC-to-ADC 1.0 kHz, 0 dBm0 1.0 kHz, 0 dBm0 1.0 kHz, +3 dBm0 to –50 dBm0 Refer to Figure 5 300 Hz to 3400 Hz; fSAMP = 64 kHz 300 Hz to 3400 Hz; fSAMP = 8 kHz 0 Hz to fSAMP/2; fSAMP = 64 kHz 300 Hz to 3400 Hz; fSAMP = 64 kHz 300 Hz to 3400 Hz; fSAMP = 64 kHz 300 Hz to 3400 Hz; fSAMP = 64 kHz PGA.


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