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AD7011 Dataheets PDF



Part Number AD7011
Manufacturers Analog Devices
Logo Analog Devices
Description CMOS/ ADC p/4 DQPSK Baseband Transmit Port
Datasheet AD7011 DatasheetAD7011 Datasheet (PDF)

a FEATURES Single +5 V Supply On-Chip ␲/4 DQPSK Modulator Modulator Bypass Analog Mode Root-Raised Cosine Tx Filters, ␣ = 0.35 Two 10-Bit D/A Converters 4th Order Reconstruction Filters Differential Analog Outputs On-Chip Ramp Up/Down Power Control On-Chip Tx Offset Calibration Dual Mode Operation, Analog and Digital Very Low Power Dissipation, 30 mW typical Power Down Mode < 10 ␮ A On-Chip Voltage Reference 24-Pin SSOP APPLICATIONS American Digital Cellular Telephony American Analog Cellular Te.

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a FEATURES Single +5 V Supply On-Chip ␲/4 DQPSK Modulator Modulator Bypass Analog Mode Root-Raised Cosine Tx Filters, ␣ = 0.35 Two 10-Bit D/A Converters 4th Order Reconstruction Filters Differential Analog Outputs On-Chip Ramp Up/Down Power Control On-Chip Tx Offset Calibration Dual Mode Operation, Analog and Digital Very Low Power Dissipation, 30 mW typical Power Down Mode < 10 ␮ A On-Chip Voltage Reference 24-Pin SSOP APPLICATIONS American Digital Cellular Telephony American Analog Cellular Telephony CMOS, ADC ␲/4 DQPSK Baseband Transmit Port AD7011 GENERAL DESCRIPTION The AD7011 is a complete low power, CMOS, π/4 DQPSK modulator with single +5 V power supply. The part is designed to perform the baseband conversion of I and Q transmit waveforms in accordance with the American Digital Cellular Telephone system (TIA IS-54). The on-chip π/4 Differential Quadrature Phase Shift Keying (DQPSK) digital modulator, which includes the root raised cosine filters, generates I and Q data in response to the transmit data stream. The AD7011 also contains ramp control envelope logic to shape the I and Q output waveforms when ramping up or down at the beginning or end of a transmit burst. Besides providing all the necessary logic to perform π/4 DQPSK modulation, the part also provides reconstruction filters to smooth the DAC outputs, providing continuous time analog outputs. The AD7011 generates differential analog outputs for both the I and Q signals. As it is a necessity for all digital mobile systems to use the lowest possible power, the device has transmit and receive power-down options. The AD7011 is housed in a space efficient 24-pin SSOP (Shrink Small Outline Package). FUNCTIONAL BLOCK DIAGRAM DGND MCLK I BIN (Q DATA) ANALOG MODE SERIAL Q INTERFACE MODULATOR BYPASS I Tx DATA (I DATA) Tx CLK (FRAME) π /4 DQPSK DIGITAL MODULATOR 10-BIT Q-DAC 10-BIT I-DAC RECONSTRUCTION FILTERS ITx ITx VDD VAA AGND CALIBRATION CIRCUITRY Q RECONSTRUCTION FILTERS QTx QTx READY AD7011 POWER 2.46V REFERENCE BOUT BYPASS MODE1 MODE2 REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AA = VDD = +5 V ؎ 10%; Test = AGND = DGND = 0 V; Digital Mode, fMCLK = 3.1104 MHz; Analog Mode, fMCLK = 2.56 MHz, POWER = VDD. All specifications are TMIN to TMAX unless otherwise noted.) AD7011–SPECIFICATIONS1 (V Parameter DIGITAL MODE TRANSMIT SPECIFICATIONS Number of Channels Output Signal Range Differential Output Range Signal Vector Magnitude2 Error Vector Magnitude2 Offset Vector Magnitude2 IS-54 Spurious Power2, 3 @ 30 kHz @ 60 kHz @ 90 kHz, 120 kHz ANALOG MODE SPECIFICATIONS No. of Channels Resolution Output Signal Range Differential Output Range DAC Update Rate SNR Differential Offset Error Group Delay Matching Between I & Q Outputs Coding Maximum and Minimum DAC Codes4 REFERENCE & CHANNEL SPECIFICATIONS Reference, VREF Reference Accuracy I and Q Gain Matching Power-Down Option LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH Output High Voltage VOL Output Low Voltage POWER SUPPLIES VDD IDD Transmit Section Active Transmit Section Powered Down5 AD7011ARS 2 VREF + VREF/4 +VREF/2 0.875 ± 7.5% 1 2.5 0.5 2.5 –35 –30 –70 –65 –75 –70 2 10 VREF ± VREF/3 ± 2VREF/3 160 60 55 ± 15 30 Twos Complement +450/–450 2.46 ±5 ± 0.2 Yes VDD – 0.9 0.9 10 10 VDD – 0.4 0.4 4.5/5.5 8 6 35 5 Units Test Conditions/Comments (ITx – ITx) and (QTx – QTx) For Each Analog Output I Channel = (ITx – ITx) and Q Channel = (QTx – QTx) Measured Differentially Volts Volts Volts max % rms typ % rms max % typ % max dB typ dB max dB typ dB max dB typ dB max (ITx – ITx) and (QTx – QTx) Bits Volts Volts kHz dB typ dB min mV max ns typ max/min Volts % dB max For Each Analog Output I Channel = (ITx – ITx) and Q Channel = (QTx – QTx) MCLK/16; fMCLK = 2.56 MHz Generating a 10 kHz Sine Wave Post Calibration Measured @ 10 kHz Power = 0 V V min V max FA max pF max V min V max V min/V max mA max mA typ µA max µA max POWER = VDD MCLK Active MCLK Inactive |IOUT| ≤ 40 µA |IOUT| ≤ 1.6 mA NOTES 1 Operating temperature ranges as follows: A Version: –40 °C to +85 °C. 2 See terminology. 3 Measured in continuous transmission and Burst Mode with the I and Q channels ramping up and down at the beginning and end of a burst. 4 Headroom must be allowed for the transmit DACs such that offsets in I & Q transmit channels can be calibrated out. Therefore, the full range of the I and Q DACs are not available to the user. The user should ensure that binary codes greater than or less than the maximum or minimum are not loa.


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