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AD7801 Dataheets PDF



Part Number AD7801
Manufacturers Analog Devices
Logo Analog Devices
Description +2.7 V to +5.5 V/ Parallel Input/ Voltage Output 8-Bit DAC
Datasheet AD7801 DatasheetAD7801 Datasheet (PDF)

a FEATURES Single 8-Bit DAC 20-Pin SOIC/TSSOP Package +2.7 V to +5.5 V Operation Internal and External Reference Capability DAC Power-Down Function Parallel Interface On-Chip Output Buffer Rail-to-Rail Operation Low Power Operation 1.75 mA max @ 3.3 V Power-Down to 1 ␮ A max @ 25؇ C APPLICATIONS Portable Battery Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators +2.7 V to +5.5 V, Parallel Input, Voltage Output 8-Bit DAC AD780.

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a FEATURES Single 8-Bit DAC 20-Pin SOIC/TSSOP Package +2.7 V to +5.5 V Operation Internal and External Reference Capability DAC Power-Down Function Parallel Interface On-Chip Output Buffer Rail-to-Rail Operation Low Power Operation 1.75 mA max @ 3.3 V Power-Down to 1 ␮ A max @ 25؇ C APPLICATIONS Portable Battery Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators +2.7 V to +5.5 V, Parallel Input, Voltage Output 8-Bit DAC AD7801 FUNCTIONAL BLOCK DIAGRAM D7 D0 INPUT REGISTER DAC REGISTER I DAC I/V VOUT WR CS CONTROL LOGIC MUX POWER-ON RESET AD7801 PD CLR LDAC REFIN ÷2 AGND VDD DGND GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7801 is a single, 8-bit, voltage out DAC that operates from a single +2.7 V to +5.5 V supply. Its on-chip precision output buffer allows the DAC output to swing rail to rail. The AD7801 has a parallel microprocessor and DSP compatible interface with high speed registers and double buffered interface logic. Data is loaded to the input register on the rising edge of CS or WR. Reference selection for the AD7801 can be either an internal reference derived from the VDD or an external reference applied at the REFIN pin. The output of the DAC can be cleared by using the asynchronous CLR input. The low power consumption of this part makes it ideally suited to portable battery operated equipment. The power consumption is less than 5 mW at 3.3 V, reducing to less than 3 µW in power-down mode. The AD7801 is available in a 20-lead SOIC and a 20-lead TSSOP package. 1. Low Power, Single Supply operation. This part operates from a single +2.7 V to +5.5 V supply and consumes typically 5 mW at 3 V, making it ideal for battery powered applications. 2. The on-chip output buffer amplifier allows the output of the DAC to swing rail to rail with a settling time of typically 1.2 µs. 3. Internal or external reference capability. 4. High speed parallel interface. 5. Power-down capability. When powered down the DAC consumes less than 1 µA at 25°C. 6. Packaged in 20-lead SOIC and TSSOP packages. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 AD7801–SPECIFICATIONS Parameter STATIC PERFORMANCE Resolution Relative Accuracy2 Differential Nonlinearity Zero-Code Error @ +25°C Full-Scale Error Zero-Code Error Drift Gain Error3 DAC REFERENCE INPUT REFIN Input Range REFIN Input Impedance OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance Short Circuit Current Power Supply Rejection Ratio4 LOGIC INPUTS Input Current VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 3.3 V @ 25°C TMIN to TMAX VDD = 5.5 V @ 25°C TMIN to TMAX IDD (Power-Down) @ 25°C TMIN to TMAX 8 ±1 ±1 3 –0.75 100 ±1 (VDD = +2.7 V to +5.5 V, Internal Reference; CL = 100 pF, RL = 10 k⍀ to VDD and GND. All specifications TMIN to TMAX unless otherwise noted.) Units Bits LSB max LSB max LSB typ LSB typ µV/°C typ % FSR typ V min/V max MΩ typ V min/V max µs max V/µs typ nV-s typ nV-s typ Ω typ mA typ %/% max µA max V max V max V min V min pF max V min/V max mA max mA max mA max mA max µA max µA max VIH = VDD and VIL = GND See Figure 18 DAC Active and Excluding Load Current VIH = VDD and VIL = GND See Figure 6 Conditions/Comments B Versions1 Guaranteed Monotonic All Zeros Loaded to DAC Register All Ones Loaded to DAC Register 1 to VDD/2 10 0 to VDD 2 7.5 1 0.2 40 14 0.0003 ± 10 0.8 0.6 2.4 2.1 7 2.7/5.5 1.55 1.75 2.35 2.5 1 2 Typically 1.2 µs 1 LSB Change Around Major Carry ∆VDD = ± 10% VDD = +5 V VDD = +3 V VDD = +5 V VDD = +3 V NOTES 1 Temperature ranges are as follows: B Version: –40 °C to +105°C 2 Relative Accuracy is calculated using a reduced code range of 15 to 245. 3 Gain Error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB. 4 Guaranteed by characterization at product release, not production tested. Specifications subject to change without notice. t1 CS t2 t3 WR t4 D7-D0 t5 t6 LDAC t7 t8 CLR Figure 1. Timing Diagram for Parallel Data Write –2– REV. 0 AD7801 TIMING CHARACTERISTICS1, 2 Parameter t1 t2 t3 t4 t5 t6 t7 t8 0 0 20 15 4.5 20 20 20 (VDD = +2.7 V to +5.5 V; GND = 0 V; Internal V DD/2 Reference. All specifications TMIN to TMAX unless otherwise noted.) Units ns min ns min ns min ns min ns min ns min ns min ns min Condition.


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