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PIC32MZ2048EFH064 Dataheets PDF



Part Number PIC32MZ2048EFH064
Manufacturers Microchip
Logo Microchip
Description 32-bit MCU
Datasheet PIC32MZ2048EFH064 DatasheetPIC32MZ2048EFH064 Datasheet (PDF)

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 32-bit MCUs (up to 2 MB Live-Update Flash and 512 KB SRAM) with FPU, Audio and Graphics Interfaces, HS USB, Ethernet, and Advanced Analog Operating Conditions Advanced Analog Features • 2.1V to 3.6V, -40ºC to +85ºC, DC to 252 MHz • 2.1V to 3.6V, -40ºC to +125ºC, DC to 180 MHz Core: 252 MHz (up to 415 DMIPS) M-Class • 16 KB I-Cache, 4 KB D-Cache • FPU for 32-bit and 64-bit floating point math • MMU for optimum embedded OS exec.

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PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 32-bit MCUs (up to 2 MB Live-Update Flash and 512 KB SRAM) with FPU, Audio and Graphics Interfaces, HS USB, Ethernet, and Advanced Analog Operating Conditions Advanced Analog Features • 2.1V to 3.6V, -40ºC to +85ºC, DC to 252 MHz • 2.1V to 3.6V, -40ºC to +125ºC, DC to 180 MHz Core: 252 MHz (up to 415 DMIPS) M-Class • 16 KB I-Cache, 4 KB D-Cache • FPU for 32-bit and 64-bit floating point math • MMU for optimum embedded OS execution • microMIPS™ mode for up to 35% smaller code size • DSP-enhanced core: - Four 64-bit accumulators - Single-cycle MAC, saturating, and fractional math - IEEE 754-compliant • Code-efficient (C and Assembly) architecture Clock Management • Programmable PLLs and oscillator clock sources • Fail-Safe Clock Monitor (FSCM) • Independent Watchdog Timers (WDT) and Deadman Timer (DMT) • Fast wake-up and start-up Power Management • Low-power modes (Sleep and Idle) • Integrated Power-on Reset (POR) and Brown-out Reset (BOR) Memory Interfaces • 50 MHz External Bus Interface (EBI) • 50 MHz Serial Quad Interface (SQI) Audio and Graphics Interfaces • Graphics interfaces: EBI or PMP • Audio data communication: I2S, LJ, and RJ • Audio control interfaces: SPI and I2C • Audio master clock: Fractional clock frequencies with USB synchronization High-Speed (HS) Communication Interfaces  (with Dedicated DMA) • USB 2.0 Hi-Speed On-The-Go (OTG) controller • 10/100 Mbps Ethernet MAC with MII and RMII interface Security Features • Crypto Engine with RNG for data encryption/decryption and authentication (AES, 3DES, SHA, MD5, and HMAC) • Advanced memory protection: - Peripheral and memory region access control • 12-bit ADC module: - 18 Msps with up to six Sample and Hold (S&H) circuits (five dedicated and one shared) - Up to 48 analog inputs - Can operate during Sleep and Idle modes - Multiple trigger sources - Six Digital Comparators and six Digital Filters • Two comparators with 32 programmable voltage references • Temperature sensor with ±2ºC accuracy Communication Interfaces • Two CAN modules (with dedicated DMA channels): - 2.0B Active with DeviceNet™ addressing support • Six UART modules (25 Mbps): - Supports up to LIN 2.1 and IrDA® protocols • Six 4-wire SPI modules (up to 50 MHz) • SQI configurable as an additional SPI module (50 MHz) • Five I2C modules (up to 1 Mbaud) with SMBus support • Parallel Master Port (PMP) • Peripheral Pin Select (PPS) to enable function remap Timers/Output Compare/Input Capture • Nine 16-bit or up to four 32-bit timers/counters • Nine Output Compare (OC) modules • Nine Input Capture (IC) modules • Real-Time Clock and Calendar (RTCC) module Input/Output • 5V-tolerant pins with up to 32 mA source/sink • Selectable open drain, pull-ups, pull-downs, and slew rate controls • External interrupts on all I/O pins • PPS to enable function remap Qualification and Class B Support • AEC-Q100 REVH (Grade 1 -40ºC to +125ºC) • Class B Safety Library, IEC 60730 • Back-up internal oscillator Debugger Development Support • In-circuit and in-application programming • 4-wire MIPS® Enhanced JTAG interface • Unlimited software and 12 complex breakpoints • IEEE 1149.2-compatible (JTAG) boundary scan • Non-intrusive hardware-based instruction trace Software and Tools Support Direct Memory Access (DMA) • Eight channels with automatic data size detection • Programmable Cyclic Redundancy Check (CRC) Packages • C/C++ compiler with native DSP/fractional and FPU support • MPLAB® Harmony Integrated Software Framework • TCP/IP, USB, Graphics, and mTouch™ middleware • MFi, Android™, and Bluetooth® audio frameworks • RTOS Kernels: Express Logic ThreadX, FreeRTOS™, OPENRTOS®, Micriµm® µC/OS™, and SEGGER embOS® Type QFN TQFP TFBGA VTLA LQFP Pin Count 64 64 100 144 100 144 124 144 I/O Pins (up to) 53 53 78 120 78 120 98 120 Contact/Lead Pitch 0.50 mm 0.50 mm 0.40 mm 0.50 mm 0.40 mm 0.65 mm 0.50 mm 0.50 mm 0.50 mm Dimensions 9x9x0.9 mm 10x10x1 mm 12x12x1 mm 14x14x1 mm 16x16x1 mm 7x7x1.2 mm 7x7x1.2 mm 9x9x0.9 mm 20x20x1.40 mm  2015-2019 Microchip Technology Inc. DS60001320G-page 1 Device Program Memory (KB) Data Memory (KB) Pins Packages Boot Flash Memory (KB) Remappable Pins Timers/ CoCampptaurree(/1) UART SPI/I2S External Interrupts(2) CAN 2.0B Crypto RNG DMA Channels (Programmable/ Dedicated) ADC (Channels) Analog Comparators USB 2.0 HS OTG I2C PMP EBI SQI RTCC Ethernet I/O Pins JTAG Trace PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320G-page 2 TABLE 1: PIC32MZ EF FAMILY FEATURES Remappable Peripherals PIC32MZ0512EFE064 0 N Y 8/12 PIC32MZ0512EFF064 512 128 2 N Y 8/16 PIC32MZ0512EFK064 PIC32MZ1024EFE064 64 TQFP, QFN 160 34 9/9/9 6 4 5 2 0 Y Y 8/18 24 2 Y 4 N Y 8/12 Y N Y Y Y 46 Y Y PIC32MZ1024EFF064 1024 256 2 .


PIC32MZ2048EFG064 PIC32MZ2048EFH064 PIC32MZ2048EFM064


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