80960JF

www.DataSheet4U.com A PRELIMINARY 80960JA/JF EMBEDDED 32-BIT MICROPROCESSOR s Pin/Code Compatible with all 80960Jx Processors s High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers (8 sets) — Nine Addressing Modes — User/Supervisor Protection Model s High Bandwidth Burst Bus — 32-Bit Multiplexed Address/Data — Programmable Memory Configuration — Selectable 8-, 16-, 32-Bit Bus Widths — Supports Unaligned Accesses — Big or Little Endian Byte Ordering s New Instructions — Conditional Add, Subtract and Select — Processor Management s Two-Way Set Associative Instruction Cache s High-Speed Interrupt Controller — 80960JA - 2 Kbyte — 80960JF - 4 Kbyte — Programmable Cache Locking — 31 Programmable Priorities — Eight Maskable Pins plus NMI — Up to 240 Vectors in Expanded Mode Mechanism s Two On-Chip Timers s Direct Mapped Data Ca...