Document
Si8430/31/35
LOW-POWER TRIPLE-CHANNEL DIGITAL ISOLATOR
Features
High-speed operation
Up to 2500 VRMS isolation
DC to 150 Mbps
60-year life at rated working
No start-up initialization required voltage
Wide Operating Supply Voltage: Precise timing (typical)
2.70–5.5 V
<10 ns worst case
Wide Operating Supply Voltage: 1.5 ns pulse width distortion
2.70–5.5V
0.5 ns channel-channel skew
d Ultra low power (typical)
2 ns propagation delay skew
e 5 V Operation:
6 ns minimum pulse width
< 1.6 mA per channel at 1 Mbps Transient Immunity 25 kV/µs
d < 6 mA per channel at 100 Mbps AEC-Q100 qualified
n 2.70 V Operation:
Wide temperature range
s < 1.4 mA per channel at 1 Mbps
–40 to 125 °C at 150 Mbps
e n < 4 mA per channel at 100 Mbps RoHS-compliant packages
High electromagnetic immunity
SOIC-16 wide body
m ig SOIC-16 narrow body
m s Applications
o e Industrial automation systems
Hybrid electric vehicles
ec D Isolated switch mode supplies
Isolated ADC, DAC Motor control Power inverters Communications systems
R w Safety Regulatory Approvals
t e UL 1577 recognized o N Up to 2500 VRMS for 1 minute
CSA component notice 5A
N r approval fo IEC 60950-1, 61010-1
(reinforced insulation)
VDE certification conformity
IEC 60747-5-2 (VDE0884 Part 2)
Ordering Information: See page 26.
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages when compared to legacy isolation technologies. The operating parameters of these products remain stable across wide temperature ranges throughout their service life, and only VDD bypass capacitors are required.
Data rates up to 150 Mbps are supported, and all devices achieve worst-case propagation delays of less than 10 ns. All products are safety certified by UL, CSA, and VDE and support withstand voltages of up to 2.5 kVRMS. These devices are available in 16-pin wide- and narrow-body SOIC packages.
Rev. 1.7 4/18
Copyright © 2018 by Silicon Laboratories
Si8430/31/35
TABLE OF CONTENTS
Si8430/31/35
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
d 3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 e 3.1. Enable Pin Causes Outputs to Go Low (Revision C Only) . . . . . . . . . . . . . . . . . . . .24 d 3.2. Power Supply Bypass Capacitors (Revision C and Revision D) . . . . . . . . . . . . . . . .24
3.3. Latch Up Immunity (Revision C Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
n s 4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 e 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 n 6. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 m ig 7. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
8. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
m s 9. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 o e 10. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10.1. 16-Pin Wide Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
c D 10.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
11. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
e 11.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 R w 11.2. .