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DISCRETE SEMICONDUCTORS
DATA SHEET
andbook, halfpage
MBD128
BF1205 Dual N-channel dual gate MOS-FET
Product specification 2003 Sep 30
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
FEATURES • Two low noise gain controlled amplifiers in a single package. One with a fully integrated bias and one with a partly integrated bias • Internal switch reduces the number of external components • Superior cross-modulation performance during AGC • High forward transfer admittance • High forward transfer admittance to input capacitance ratio. APPLICATIONS • Gain controlled low noise amplifiers for VHF and UHF applications with 5 V supply voltage, such as digital and analog television tuners and professional communications equipment. DESCRIPTION The BF1205 is a combination of two equal dual gate MOS-FET amplifiers with shared source and gate 2 leads and an integrated switch. The integrated switch is operated by the gate 1 bias of amplifier b. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross-modulation performance during AGC. Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor is encapsulated in SOT363 micro-miniature plastic package. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME BF1205 − DESCRIPTION Plastic surface mounted package; 6 leads
1 2 Top view 3 g1 (a) g2
handbook, halfpage
BF1205
PINNING - SOT363 PIN 1 2 3 4 5 6 gate 1 (a) gate 2 gate 1 (b) drain (b) source drain (a) DESCRIPTION
d (a) 4
s
d (b)
6
5
AMP a
AMP b
g1 (b)
MGX429
Marking code: L4-.
Fig.1 Simplified outline and symbol.
VERSION SOT363
2003 Sep 30
2
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS
BF1205
MIN. TYP. MAX. UNIT − − − − − 31 1.8 2.0 20 1.2 1.4 102 105 −
Per MOS-FET; unless otherwise specified VDS ID Ptot yfs Cig1-ss Crss NF Xmod drain-source voltage drain current (DC) total power dissipation forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure cross-modulation Ts ≤ 102 °C; temperature at the soldering point of the source lead ID = 12 mA amp. a: f = 1 MHz amp. b: f = 1 MHz f = 1 MHz amp. a: f = 800 MHz amp. b: f = 800 MHz amp. a: input level for k = 1% at 40 dB AGC amp. b: input level for k = 1% at 40 dB AGC Tj junction temperature CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS − − − − Ts ≤ 102 °C; note − −65 − MIN. MAX. UNIT 10 30 200 40 2.3 2.5 − 1.9 2.1 − − 150 V mA mW mS pF pF fF dB dB dBµV dBµV °C
− 26 − − − − − 98 100 −
Per MOS-FET; unless otherwise specified VDS ID IG1 IG2 Ptot Tstg Tj Note 1. Ts is the temperature at the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL Rth j-s PARAMETER thermal resistance from junction to soldering point VALUE 240 UNIT K/W drain-source voltage drain current (DC) gate 1 current gate 2 current total power dissipation storage temperature junction temperature 10 30 ±10 ±10 200 +150 150 V mA mA mA mW °C °C
2003 Sep 30
3
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
handbook, halfpage
250 Ptot 200
MGS359
(mW)
150
100
50
0 0 50 100 150 Ts (°C) 200
Fig.2 Power derating curve.
STATIC CHARACTERISTICS Tj = 25 °C; per MOS-FET; unless otherwise specified. SYMBOL V(BR)DSS V(BR)G1-SS V(BR)G2-SS V(F)S-G1 V(F)S-G2 VG1-S(th) VG2-S(th) IDSX PARAMETER drain-source breakdown voltage gate-source breakdown voltage gate-source breakdown voltage forward source-gate voltage forward source-gate voltage gate-source threshold voltage gate-source threshold voltage drain-source current CONDITIONS MIN. MAX. − − 10 10 1.5 1.5 1 1.0 16 16 50 50 20 UNIT V V V V V V V V mA mA nA nA nA amp. a: VG1-S = VG2-S = 0 V; ID = 10 µA 10 amp. b: VG1-S = VG2-S = 0 V; ID = 10 µA 7 VGS = VDS = 0 V; IG1-S = 10 mA VGS = VDS = 0 V; IG2-S = 10 mA VG2-S = VDS = 0 V; IS-G1 = 10 mA VG1-S = VDS = 0 V; IS-G2 = 10 mA VDS = 5 V; VG2-S = 4 V; ID = 100 µA VDS = 5 V; VG1-S = 5 V; ID = 100 µA amp. a: VG2-S = 4 V; VDS = 5 V; RG1 = 150 kΩ; note 1 amp. b: VG2-S = 4 V; VDS = 5 V; RG1 = 150 kΩ; note 2 IG1-S IG2-S Note 1. RG1 connects gate 1 (b) to VGG = 0 V (see Fig.4). 2. RG1 connects gate 1 (b) to VGG = 5 V (see Fig.4). gate cut-off current gate cut-off current amp. a: VG1-S = 5 V; VG2-S = VDS = 0 V amp. b: VG1-S = 5 V; VG2-S = VDS = 0 V VG2-S = 4 V; VG1-S = VDS = 0 V 6 6 0.5 0.5 0.3 0.4 8 8 − − −
2003 Sep 30
4
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
handbook, halfpage
16
MGX430
ID (mA) 12
(1)
handbook, halfpage
(2)
g1 (a) g2
d (a) s d (b) R G1
(3)
8
g1 (b)
.