Document
Silicon N-Channel MOSFET Tetrode
• For low noise, high gain controlled input stages up to 1 GHz
• Operating voltage 5V • Integrated biasing network • Pb-free (RoHS compliant) package1) • Qualified according AEC Q101
BF1005...
AGC
RF Input
Drain RF Output G2 + DC G1
GND
ESD (Electrostatic discharge) sensitive device, observe handling precaution!
Type
Package
Pin Configuration
BF1005
SOT143 1=S 2=D 3=G2 4=G1 -
-
BF1005R
SOT143R 1=D 2=S 3=G1 4=G2 -
-
Marking MZs MZs
Maximum Ratings
Parameter
Symbol
Value
Unit
Drain-source voltage Continuous drain current Gate 1/ gate 2-source current Gate 1 (external biasing) Total power dissipation TS ≤ 76 °C Storage temperature Channel temperature
VDS ID ±IG1/2SM +VG1SE Ptot
Tstg Tch
8 25 10 3 200
-55 ... 150 150
V mA
V mW
°C
1Pb-containing package may be available upon special request
Note: It is not recommended to apply external DC-voltage on Gate 1 in active mode.
1 2007-04-20
BF1005...
Thermal Resistance Parameter Channel - soldering point1)
Symbol Rthchs
Value ≤ 370
Unit K/W
Electrical Characteristics at TA = 25°C, unless otherwise specified
Parameter
Symbol
Values
Unit
min. typ. max.
DC Characteristics
Drain-source breakdown voltage ID = 650 µA, VG1S = 0 , VG2S = 0 Gate1-source breakdown voltage +IG1S = 10 mA, VG2S = 0 , VDS = 0 Gate2 source breakdown voltage ±IG2S = 10 mA, VG1S = 0 , VDS = 0 Gate1-source leakage current VG1S = 0 , VG2S = 6 V Gate 2 source leakage current ±VG2S = 8 V, VG1S = 0 , VDS = 0 Drain current VDS = 5 V, VG1S = 0 , VG2S = 4 V Operating current (selfbiased) VDS = 5 V, VG2S = 4 V Gate2-source pinch-off voltage VDS = 5 V, ID = 100 µA
V(BR)DS
12 -
-V
+V(BR)G1SS 8
- 12
±V(BR)G2SS 8
- 13
+IG1SS
- 100 - µA
±IG2SS
- - 50 nA
IDSS
- - 1.5 mA
IDSO
8 10 16
VG2S(p)
- 1 -V
1For calculation of RthJA please refer to Application Note Thermal Resistance
2 2007-04-20
BF1005...
Electrical Characteristics at TA = 25°C, unless otherwise specified
Parameter
Symbol
Values
Unit
min. typ. max.
AC Characteristics (verified by random sampling)
Forward transconductance VDS = 5 V, VG2S = 4.5 V Gate1 input capacitance VDS = 5 V, VG2S = 4 V, f = 10 MHz Output capacitance VDS = 5 V, VG2S = 4 V, f = 10 MHz Power gain (self biased) VDS = 5 V, VG2S = 4 V, f = 800 MHz Noise figure
gfs Cg1ss Cdss Gp F
20 24
- mS
- 2.1 2.5 pF
- 1.3 -
17 19
- dB
- 1.6 2.5 dB
VDS = 5 V, VG2S = 4 V, f = 800 MHz Gain control range VDS = 5 V, VG2S = 4V ...0V, f = 800 GHz
∆Gp
40 50
-
3 2007-04-20
BF1005...
Total power dissipation Ptot = ƒ(TS) BF1005, BF1005R
Total power dissipation Ptot = ƒ(TS) BF1005W
ID Ptot |S21|² Ptot
220 mW
180 160 140 120 100
80 60 40 20
0 0 15 30 45 60 75 90 105 120 °C 150
TS
Drain current ID = ƒ(VG2S)
220 mA
180 160 140 120 100
80 60 40 20
0 0 15 30 45 60 75 90 105 120 °C 150
TS
Insertion power gain |S21|² = ƒ(VG2S)
12 mA
10 9 8 7 6 5 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 V 5
VG2S
10 dB
0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55
0 0.5 .