CMOS Gate Array
3/3
$0,+* PLFURQ &026 *DWH $UUD\
Description PLP3 is a programmable pull-up/pull-down buffer piece.
Logic Symbo...
Description
3/3
$0,+* PLFURQ &026 *DWH $UUD\
Description PLP3 is a programmable pull-up/pull-down buffer piece.
Logic Symbol
Truth Table
PLP3
PADM
ma mb
MA MB
PADM Function
L L Pull-down
HH
Pull-up
HL
Tristate
L H Tristate
HDL Syntax Verilog .................... PLP3 inst_name (PADM, MA, MB); VHDL...................... inst_name: PLP3 port map (PADM, MA, MB);
Power Characteristics
Parameter Static IDD (TJ = 85°C) EQLpd
See page 2-15 for power equation.
Value TBD 146.8
Units nA Eq-load
®
Pin Loading Load
MA 2.1 eql MB 1.8 eql
Pad Logic
4-52
...
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