ODTSXN16

2'76;1[[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Description ODTSXNxx is a family of 4 to 24 mA, non-inverting, TTL-level, output buffer pieces with N-channel open-drains (pulldown) and controlled slew rate outputs. Logic Symbol Truth Table ODTSXNxx A PADM A PADM LL HZ Z = High Impedance Pad Logic HDL Syntax Verilog .................... ODTSXNxx inst_name (PADM, A); VHDL...................... inst_name: ODTSXNxx port map (PADM, A); Pin Loading Pin Name A (eq-load) PADM (pF) ODTSXN04 8.1 4.90 ODTSXN08 8.1 4.90 Load ODTSXN12 8.1 4.90 ODTSXN16 8.1 4.90 ODTSXN24 8.1 4.90 Power Characteristics Cell Output Drive (mA) ODTSXN04 4 ODTSXN08 8 ODTSXN12 12 ODTSXN16 16 ODTSXN24 24 a. See page 2-15 for power equation. Power Characteristicsa Static IDD (TJ = 85°C) (nA) TBD EQLpd (Eq-load) 164.3 TBD 172.6 TBD 180.2 TBD 188.3 TBD 200.2 Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Capacitive Load (pF) 15 ODTSXN04 From: A To: PADM ...