ODPSXE24

2'36;( ® $0,+*  PLFURQ &026 *DWH $UUD\ Description ODPSXE24 is a 33 MHz PCI, non-inverting, tristate buffer piece with active low enable and controlled slew rate output. Logic Symbol Truth Table Pin Loading ODPSXE24 EN A PCI SL PADM EN A PADM LL L LH H HX Z A EN PADM Load 8.2 pF 5.5 pF 4.93 pF HDL Syntax Verilog .................... ODPSXE24 inst_name (PADM, A, EN); VHDL...................... inst_name: ODPSXE24 port map (PADM, A, EN); Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 229.2 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Delay (ns) From To Parameter 15 A PADM tPLH tPHL 1.50 2.08 tHZ 3.47 EN PADM tLZ tZH 2.49 1.41 tZL 1.46 Delay will vary with input conditions. See page 2-17 for interconnect estimates. 50 1.92 2.70 1.83 2.37 Capacitive Load (pF) 100 2.41 3.62 2.37 3.45 200 3.33 5.52 3.42 5.46 300 (max) 4.28 7.49 4.43 7.46 Pad Logic...