CMOS Gate Array
Core Logic
,7'[
$0,+* PLFURQ &026 *DWH $UUD\
Description ITD1x is a family of inverting internal tristate buffer...
Description
Core Logic
,7'[
$0,+* PLFURQ &026 *DWH $UUD\
Description ITD1x is a family of inverting internal tristate buffers with active high enable.
Logic Symbol
Truth Table
ITDx E
A QN E
A QN
E A QN LXZ HLH HH L Z = High Impedance
HDL Syntax Verilog .................... ITDx inst_name (QN, A, E); VHDL...................... inst_name: ITDx port map (QN, A, E);
Pin Loading
Pin Name
A E QN
ITD1 1.0 1.6 0.6
Equivalent Loads ITD2 ITD4 2.1 4.3 2.0 3.1 0.6 2.5
ITD6 6.4 4.1 3.8
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
ITD1 2.0
TBD
2.9
ITD2 3.0
TBD
4.7
ITD4 5.0
TBD
7.9
ITD6 7.0
TBD
11.5
a. See page 2-15 for power equation.
3-132
®
Core Logic
,7'[
®
$0,+* PLFURQ &026 *DWH $UUD\
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Number of Equivalent Loads
1
From: A ITD1 To: QN
tPLH tPHL
From: E To: QN
tZH tZL
Number of Equivalent Loads
0.20 0.18
...
Similar Datasheet