CMOS Gate Array
Core Logic
'/[
$0,+* PLFURQ &026 *DWH $UUD\
Description DL64x is a family of transparent, buffered D latches w...
Description
Core Logic
'/[
$0,+* PLFURQ &026 *DWH $UUD\
Description DL64x is a family of transparent, buffered D latches with active low gate transparency. RESET is active low.
Logic Symbol
Truth Table
DL64x
DQ G
Q R
RN D GN Q QN HL L LH HH L H L H X H NC NC LXXLH
NC = No Change
HDL Syntax Verilog .................... DL64x inst_name (Q, QN, D, GN); VHDL...................... inst_name: DL64x port map (Q, QN, D, GN);
Pin Loading
Pin Name
D GN RN
DL641 1.0 1.0 1.0
Equivalent Loads
DL642
DL644
1.0 1.0
1.0 1.0
1.0 1.0
DL646 1.0 1.0 1.0
Size And Power Characteristics
Cell
DL641 DL642
Equivalent Gates
5.0 7.0
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
TBD
11.3
TBD
13.4
DL644 DL646
11.0 14.0
TBD TBD
28.8 35.7
a. See page 2-15 for power equation.
®
3-106
Core Logic
®
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Number of Equivalent Loads
1
DL641
From: D To: Q
tPLH tPHL
From: D To: QN
tPLH tPHL
F...
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