Core Logic
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Description DL63x is a family of transparent, buffered D latches with active low gate transparency and without SET or RESET.
Logic Symbol
Truth Table
DL63x DQ G
Q
D GN Q QN L L LH HLHL X H NC NC
NC = No Change
HDL Syntax Verilog DL63x inst_name (Q, QN, D, GN); VHDL.. inst_name: DL63x port map (Q, QN, D, GN);
Pin Loading
Pin Name D GN
DL631 1.1 1.0
Equivalent Loads
DL632
DL634
1.0 1.0
1.0 .