DF221

Core Logic ') ® $0,+*  PLFURQ &026 *DWH $UUD\ Description DF221 is a static, master-slave, multiplexed scan D flip-flop. SET is asynchronous and active low. Output is unbuffered and changes state on the rising edge of the clock. Logic Symbol DF221 DS C SD SE Q Truth Table C ↑ ↑ ↑ ↑ X L D SD SE SN HX L H LXLH XHHH X LHH XXXL XXXH NC = No Change Q H L H L H NC Pin Loading Equivalent Load C 1.0 D 1.0 SD 1.0 SE 2.1 SN 2.1 Equivalent Gates ................... 11.0 HDL Syntax Verilog .................... DF221 inst_name (Q, C, D, SD, SE, SN); VHDL...................... inst_name: DF221 port map (Q, C, D, SD, SE, SN); Size And Power Characteristics Parameter Value Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. TBD 19.5 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process From Delay (ns) To Parameter 1 Number of Equivalent Loads 258 C Q tPLH tPHL 0.67 0.64 0.70 0.69 SN Q tPLH 0.15 0.18 Delay will...