Core Logic
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Description
DF021 is a static, master-slave D flip-flop. SET is asynchronous and active low. Output is unbuffered and changes state on the rising edge of the clock.
Logic Symbol
Truth Table
Pin Loading
DF021
DSQ C
SN D C Q
L XXH HL ↑L HH ↑H H X L NC
NC = No Change
Equivalent Load
D 1.0 C 1.0 SN 2.1
Equivalent Gates .... 7.0
HDL Syntax Verilog....DF021 inst_name (Q, C, D, SN); VHDL.. i.