Core Logic
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Description
DF00x is a family of static, master-slave D flip-flops without SET or RESET. Output is unbuffered and changes state on the rising edge of the clock.
Logic Symbol
Truth Table
DF00x
DQ C
DCQ H↑H L↑L X L NC
NC = No Change
HDL Syntax Verilog .................... DF00x inst_name (Q, C, D); V...
