Core Logic
%5[
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$0,+* PLFURQ &026 *DWH $UUD\
Description BR0x is a family of non-inverting bus receivers with a single output to be used as the output of tristate busses.
Logic Symbol
Truth Table
BR0x
AQ AQ
AQ LL HH
HDL Syntax Verilog .................... BR0x inst_name (Q, A); VHDL...................... inst_name: BR0x port map (Q, A);
Pin ...
