CMOS Gate Array
Core Logic
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®
$0,+* PLFURQ &026 *DWH $UUD\
Description AN2x is a family of AND-NOR circuits consisting of on...
Description
Core Logic
$1[
®
$0,+* PLFURQ &026 *DWH $UUD\
Description AN2x is a family of AND-NOR circuits consisting of one 2-input AND gate into a 2-input NOR gate.
Logic Symbol
Truth Table
A AN2x B
Q
A B CQ HHX L
XXHL C
All other combinations H
HDL Syntax Verilog .................... AN2x inst_name (Q, A, B, C); VHDL...................... inst_name: AN2x port map (Q, A, B, C);
Pin Loading
Pin Name
A B C
AN21 1.0 1.0 1.0
Equivalent Loads
AN22
AN24
1.0 1.0
1.0 1.0
1.0 1.0
AN26 2.1 2.1 1.0
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
AN21
2.0
TBD
2.1
AN22
3.0
TBD
6.4
AN24
4.0
TBD
7.7
AN26
7.0
TBD
14.6
a. See page 2-15 for power equation.
3-9
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$0,+* PLFURQ &026 *DWH $UUD\
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
AN21
Number of Equivalent Loads
From: Any Input To: Q
tPLH tPHL
Number of Equivalent Loads
1
0.15 0.16
1
2
0.21 ...
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