High-Density EE CMOS Programmable Logic
FINAL
COM’L: -7/10/12/15/20, Q-12/15/20
MACH210A-7/10/12
MACH210-12/15/20
MACH210AQ-12/15/20
High-Density EE CMOS P...
Description
FINAL
COM’L: -7/10/12/15/20, Q-12/15/20
MACH210A-7/10/12
MACH210-12/15/20
MACH210AQ-12/15/20
High-Density EE CMOS Programmable Logic
IND: -12/14/18/24
Lattice Semiconductor
DISTINCTIVE CHARACTERISTICS
44 Pins 64 Macrocells
7.5 ns tPD Commercial 12 ns tPD Industrial
133 MHz fCNT 38 Inputs; 210A Inputs have built-in pull-up resistors
Peripheral Component Interconnect (PCI) compliant
32 Outputs
64 Flip-flops; 2 clock choices
4 “PAL22V16” blocks with buried macrocells
Pin-compatible with MACH110, MACH111, MACH211, and MACH215
GENERAL DESCRIPTION
The MACH210 is a member of the high-performance EE CMOS MACH 2 device family. This device has approximately six times the logic macrocell capability of the popular PAL22V10 without loss of speed.
The MACH210 consists of four PAL blocks interconnected by a programmable switch matrix. The four PAL blocks are essentially “PAL22V16” structures complete with product-term arrays and programmable macrocells, including additional buried ...
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