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BS616LV2013 Dataheets PDF



Part Number BS616LV2013
Manufacturers Brilliance Semiconductor
Logo Brilliance Semiconductor
Description Very Low Power/Voltage CMOS SRAM 128K X 16 bit
Datasheet BS616LV2013 DatasheetBS616LV2013 Datasheet (PDF)

B SI „ FEATURES Very Low Power/Voltage CMOS SRAM 128K X 16 bit „ DESCRIPTION BS616LV2013 • Very low operation voltage : 2.4 ~ 3.6V • Very low power consumption : Vcc = 3.0V C-grade: 20mA (Max.) operating current I -grade: 25mA (Max.) operating current 0.1uA (Typ.) CMOS standby current • High speed access time : -70 70ns (Max.) at Vcc = 3.0V -10 100ns (Max.) at Vcc = 3.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data ret.

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B SI „ FEATURES Very Low Power/Voltage CMOS SRAM 128K X 16 bit „ DESCRIPTION BS616LV2013 • Very low operation voltage : 2.4 ~ 3.6V • Very low power consumption : Vcc = 3.0V C-grade: 20mA (Max.) operating current I -grade: 25mA (Max.) operating current 0.1uA (Typ.) CMOS standby current • High speed access time : -70 70ns (Max.) at Vcc = 3.0V -10 100ns (Max.) at Vcc = 3.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options • I/O Configuration x8/x16 selectable by LB and UB pin „ PRODUCT FAMILY PRODUCT FAMILY BS616LV2013DC BS616LV2013EC BS616LV2013TC BS616LV2013AC BS616LV2013DI BS616LV2013EI BS616LV2013TI BS616LV2013AI OPERATING TEMPERATURE Vcc RANGE The BS616LV2013 is a high performance, very low power CMOS Static Random Access Memory organized as 131,072 words by 16 bits and operates from a wide range of 2.4V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.1uA and maximum access time of 70/100ns in 3V operation. Easy memory expansion is provided by active LOW chip enable(CE), active LOW output enable(OE) and three-state output drivers. The BS616LV2013 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV2013 is available in DICE form, JEDEC standard 44-pin TSOP Type II package , JEDEC standard 48-pin TSOP Type I package and 48-ball BGA package. SPEED ( ns ) Vcc=3.0V ( ICCSB1, Max ) Vcc=3.0V POWER DISSIPATION STANDBY Operating ( ICC, Max ) Vcc=3.0V PKG TYPE DICE TSOP2-44 TSOP1-48 BGA-48-0608 DICE TSOP2-44 TSOP1-48 BGA-48-0608 +0 C to +70 C O O 2.4V ~3.6V 70/100 0.7uA 20mA -40 O C to +85 O C 2.4V ~ 3.6V 70/100 1.5uA 25mA „ PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VCC GND DQ4 DQ5 DQ6 DQ7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 GND VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 NC „ BLOCK DIAGRAM A8 A13 A15 A16 A14 A12 A7 A6 A5 A4 2048 DQ0 16 Data Input Buffer 16 Column I/O Address Input Buffer 20 Row Decoder 1024 Memory Array 1024 x 2048 BS616LV2013EC BS616LV2013EI 1 2 3 4 5 6 A B C D E F G H LB D8 D9 VSS VCC OE UB D10 D11 D12 D13 A0 A3 A5 N.C. N.C. A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 A2 N.C. D0 . . . . DQ15 . . . . Write Driver Sense Amp 128 Column Decoder 16 Data Output 16 Buffer CE D1 D3 D4 D5 WE A11 CE D2 VCC VSS Vcc Gnd WE OE UB LB Control 14 Address Input Buffer A11 A9 A3 A2 A1 A0 A10 D14 D15 N.C. D6 D7 N.C. N.C. A8 Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. R0201-BS616LV2013 48-ball BGA top view 1 Revision 2.5 April 2002 BSI „ PIN DESCRIPTIONS BS616LV2013 Name A0-A16 Address Input CE Chip Enable Input Function These 17 address inputs select one of the 131,072 x 16-bit words in the RAM. CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. Lower byte and upper byte data input/output control pins. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground WE Write Enable Input OE Output Enable Input LB and UB Data Byte Control Input DQ0 - DQ15 Data Input/Output Ports Vcc Gnd „ TRUTH TABLE MODE Not selected (Power Down) Output Disabled Read CE H L L WE X H H OE X H L LB X X L H L L Write L L X H L UB X X L L H L L H DQ0~DQ7 High Z High Z Dout High Z Dout Din X Din DQ8~DQ15 High Z High Z Dout Dout High Z Din Din X Vcc CURRENT ICCSB, ICCSB1 ICC ICC ICC ICC ICC ICC ICC R0201-BS616LV2013 2 Revision 2.5 April 2002 BSI „ ABSOLUTE MAXIMUM RATINGS(1) SYMBOL V TERM T BIAS T STG PT I OUT PARAMETER Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current BS616LV2013 „ OPERATING RANGE UNITS V O RATING -0.5 to Vcc+0.5 -40 to +125 -60 to +150 1.0 20 RANGE Commercial Industrial AMBIENT TEMPERATURE 0 O C to +70 O C -40 C to +85 C O O Vcc 2.4V ~ 3.6V 2.4V ~ 3.6V C C O W mA „ CAPACITANCE (1) (TA = 25oC, f =.


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