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LPC54628 Dataheets PDF



Part Number LPC54628
Manufacturers NXP
Logo NXP
Description 32-bit ARM Cortex-M4 microcontroller
Datasheet LPC54628 DatasheetLPC54628 Datasheet (PDF)

LPC546xx 32-bit ARM Cortex-M4 microcontroller; up to 512 KB flash and 200 kB SRAM; High-speed USB device/host + PHY; Full-speed USB device/host; Ethernet AVB; LCD; EMC; SPIFI; CAN FD, SDIO; SHA; 12-bit 5 Msamples/s ADC; DMIC subsystem Rev. 2.8 — 8 September 2020 Product data sheet 1. General description The LPC546xx is a family of ARM Cortex-M4 based microcontrollers for embedded applications featuring a rich peripheral set with very low power consumption and enhanced debug features. The ARM.

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LPC546xx 32-bit ARM Cortex-M4 microcontroller; up to 512 KB flash and 200 kB SRAM; High-speed USB device/host + PHY; Full-speed USB device/host; Ethernet AVB; LCD; EMC; SPIFI; CAN FD, SDIO; SHA; 12-bit 5 Msamples/s ADC; DMIC subsystem Rev. 2.8 — 8 September 2020 Product data sheet 1. General description The LPC546xx is a family of ARM Cortex-M4 based microcontrollers for embedded applications featuring a rich peripheral set with very low power consumption and enhanced debug features. The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point processor is integrated into the core. The LPC546xx family includes up to 512 KB of flash, 200 KB of on-chip SRAM, up to 16 kB of EEPROM memory, a quad SPI Flash Interface (SPIFI) for expanding program memory, one high-speed and one full-speed USB host and device controller, Ethernet AVB, LCD controller, Smart Card Interfaces, SD/MMC, CAN FD, an External Memory Controller (EMC), a DMIC subsystem with PDM microphone interface and I2S, five general-purpose timers, SCTimer/PWM, RTC/alarm timer, Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), ten flexible serial communication peripherals (USART, SPI, I2S, I2C interface), Secure Hash Algorithm (SHA), 12-bit 5.0 Msamples/sec ADC, and a temperature sensor. 2. Features and benefits  ARM Cortex-M4 core (version r0p1):  ARM Cortex-M4 processor, running at a frequency of up to 220 MHz.  The LPC5460x/61x devices operate at CPU frequencies of up to 180 MHz. The LPC54628 device operates at CPU frequencies of up to 220 MHz.  Floating Point Unit (FPU) and Memory Protection Unit (MPU).  ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).  Non-maskable Interrupt (NMI) input with a selection of sources.  Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators, and four watch points. Includes Serial Wire Output and ETM Trace for enhanced debug capabilities, and a debug timestamp counter.  System tick timer. NXP Semiconductors LPC546xx 32-bit ARM Cortex-M4 microcontroller LPC546xx Product data sheet  On-chip memory:  Up to 512 KB on-chip flash program memory with flash accelerator and 256 byte page erase and write.  Up to 200 KB total SRAM consisting of 160 KB contiguous main SRAM and an additional 32 KB SRAM on the I&D buses. 8 KB of SRAM bank intended for USB traffic.  16 KB of EEPROM.  ROM API support:  Flash In-Application Programming (IAP) and In-System Programming (ISP).  ROM-based USB drivers (HID, CDC, MSC, and DFU). Flash updates via USB.  Booting from valid user code in flash, USART, SPI, and I2C.  Legacy, Single, and Dual image boot.  OTP API for programming OTP memory.  Random Number Generator (RNG) API.  Serial interfaces:  Flexcomm Interface contains up to ten serial peripherals. Each Flexcomm Interface can be selected by software to be a USART, SPI, or I2C interface. Two Flexcomm Interfaces also include an I2S interface. Each Flexcomm Interface includes a FIFO that supports USART, SPI, and I2S if supported by that Flexcomm Interface. A variety of clocking options are available to each Flexcomm Interface and include a shared fractional baud-rate generator.  I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to 1Mbit/s and with multiple address recognition and monitor mode. Two sets of true I2C pads also support High Speed Mode (3.4 Mbit/s) as a slave.  Two ISO 7816 Smart Card Interfaces with DMA support.  USB 2.0 high-speed host/device controller with on-chip high-speed PHY.  USB 2.0 full-speed host/device controller with on-chip PHY and dedicated DMA controller supporting crystal-less operation in device mode using software library. See Technical note TN00032 for more details.  SPIFI with XIP feature uses up to four data lines to access off-chip SPI/DSPI/QSPI flash memory at a much higher rate than standard SPI or SSP interfaces.  Ethernet MAC with MII/RMII interface with Audio Video Bridging (AVB) support and dedicated DMA controller.  Two CAN FD modules with dedicated DMA controller.  Digital peripherals:  DMA controller with 30 channels and up to 24 programmable triggers, able to access all memories and DMA-capable peripherals.  LCD Controller supporting both Super-Twisted Nematic (STN) and Thin-Film Transistor (TFT) displays. It has a dedicated DMA controller, selectable display resolution (up to 1024 x 768 pixels), and supports up to 24-bit true-color mode.  External Memory Co.


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