Document
DISCRETE SEMICONDUCTORS
DATA SHEET
BST80 N-channel enhancement mode vertical D-MOS transistor
Product specification Supersedes data of April 1995 File under Discrete Semiconductors, SC13b 1997 Jun 20
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
FEATURES • Low drain-source on-state resistance • Direct interface to C-MOS, TTL, etc. • High-speed switching • No secondary breakdown. APPLICATIONS • Thin and thick film circuits • Relay, high-speed and line transformer drivers.
g
handbook, halfpage
BST80
PINNING - SOT89 PIN 1 2 3 SYMBOL s d g source drain gate DESCRIPTION
d
DESCRIPTION N-channel enhancement mode vertical D-MOS transistor in a SOT89 package.
1 Bottom view 2 3
MAM355
s
Marking code: KM
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA SYMBOL VDS VGSO ID Ptot RDSon yfs PARAMETER drain-source voltage (DC) gate-source voltage (DC) drain current (DC) total power dissipation drain-source on-state resistance forward transfer admittance Tamb ≤ 25 °C ID = 500 mA; VGS = 10 V ID = 500 mA; VDS = 15 V open drain CONDITIONS − − − − 2 300 TYP. MAX. 80 ±20 500 1 3 − V V mA W Ω mS UNIT
1997 Jun 20
2
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDS VGSO ID IDM Ptot Tstg Tj PARAMETER drain-source voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature junction temperature Tamb ≤ 25 °C; note 1 open drain CONDITIONS − − − − − −65 − MIN.
BST80
MAX. 80 ±20 500 1 1 +150 150 V V
UNIT
mA A W °C °C
THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient note 1 CONDITIONS VALUE 125 UNIT K/W
Note to the Limiting values and Thermal characteristics 1. Device mounted on a ceramic substrate; area 2.5 cm2; thickness 0.7 mm. CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL V(BR)DSS VGSth IDSS IGSS RDSon yfs Ciss Coss Crss ton toff PARAMETER drain-source breakdown voltage gate-source threshold voltage drain-source leakage current gate leakage current drain-source on-state resistance forward transfer admittance input capacitance output capacitance reverse transfer capacitance CONDITIONS VGS = 0; ID = 10 µA VDS = VGS ; ID = 1 mA VDS = 60 V; VGS = 0 VDS = 0; VGS = ±20 V VGS = 10 V; ID = 500 mA ID = 500 mA; VDS = 15 V VDS = 10 V; VGS = 0; f = 1 MHz VDS = 10 V; VGS = 0; f = 1 MHz VDS = 10 V; VGS = 0; f = 1 MHz VGS = 0 to 10 V; VDD = 50 V; ID = 500 mA VGS = 10 to 0 V; VDD = 50 V; ID = 500 mA MIN. 80 1.5 − − − − − − − − − TYP. − − − − 2 300 45 30 8 − − MAX. UNIT − 3.5 1 ±100 3 − 60 45 12 V V µA nA Ω mS pF pF pF
Switching times (see Figs 2 and 3) turn-on time turn-off time 10 15 ns ns
1997 Jun 20
3
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
BST80
handbook, halfpage
VDD = 50 V
handbook, .