HD74CDC2510B

HD74CDC2510B 3.3-V Phase-lock Loop Clock Driver REJ03D0826-0900 (Previous: ADE-205-219G) Rev.9.00 Apr 07, 2006 Description The HD74CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The HD74CDC2510B operates at 3.3 V VCC and is designed to drive up to five clock loads per output. Bank of outputs provide ten low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock. Bank of outputs can be enabled or disabled via the control (G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the HD74CDC2510B does not require exter...