3.3-V 10-bit Flip Flops with Dual Outputs
The flip flops of the HD74ALVCH16820 are edge triggered D-type flip flops. On the positive transition of
the clock (CLK) input, the device provides true data at the Q outputs. A buffered output enable (OE) input
can be used to place the ten outputs in either a normal logic state (high or low logic level) or a high
impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly.
The high impedance state and increased drive provide the capability to drive bus lines without need for
interface or pullup components. OE input does not affect the internal operation of the flip flops. Old data
can be retained or new data can be entered while the outputs are in the high impedance state. Active bus
hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V)
• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
Rev.4.00, Oct.02.2003, page 1 of 11