HD74ALVCH162501

HD74ALVCH162501 18-bit Universal Bus Transceivers with 3-state Outputs REJ03D0047-0200Z (Previous ADE-205-182 (Z) ) Rev 2.00 Oct.02.2003 Description Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A to B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A bus data is stored in the latch flip flop on the low to high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high, and OEBA is active low). Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include...