4-bit Parallel-Access Shift Register
(Previous ADE-205-380 (Z))
This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct
overriding clear. This shift register can operate in two modes: Parallel load; Shift from Q0 towards Q3.
Parallel loading is accomplished by applying the four bits of data, and taking the PE Input low. The data is loaded into
the associated flip-flops and appears at the outputs after the positive transition of the CP input. During parallel loading,
serial data flow is inhibited. Serial shifting occurs synchronously when the PE input is high. Serial data for this mode
is entered at the J-K inputs. These inputs allow the first stage to perform as a J-K or toggle flip-flop as shown in the
• Shift Right and Parallel Load Capability
• J-K (D-Type) Inputs to First Stage
• Complement Output from Last Stage
• Asynchronous Master Reset
• Outputs Source/Sink 24 mA
• Ordering Information
Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity)
HD74AC195FPEL SOP-16 pin (JEITA) FP-16DAV
EL (2,000 pcs/reel)
HD74AC195RPEL SOP-16 pin (JEDEC) FP-16DNV
EL (2,500 pcs/reel)
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Rev.2.00, Jul.16.2004, page 1 of 7