4-bit Bidirectional Unviersal Shift Register
(Previous ADE-205-379 (Z))
This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a
shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, operating mode control
inputs, and a direct overriding clear line. The register has four destinct modes of operation: parallel (broadside) load,
shift right (in the direction Q0 toward Q3); shift left; inhibit clock (do nothing).
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0
and S1, high. The data are loaded into their respective flip-flops and appear at the output after the positive transition of
the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising
edge of the clock pulse when S0 is high and S1 is low. Serial date for this mode is entered at the shift right data input.
When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shifts left serial input.
Clocking of the flip-flops is inhibited when both mode control inputs are low. The mode control inputs should be
changed only when the clock input is high.
• Asynchronous Master Reset
• Hole (Do Nothing) Mode
• Outputs Source/Sink 24 mA
• Ordering Information
Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity)
HD74AC194FPEL SOP-16 pin (JEITA) FP-16DAV
EL (2,000 pcs/reel)
HD74AC194RPEL SOP-16 pin (JEDEC) FP-16DNV
EL (2,500 pcs/reel)
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Rev.2.00, Jul.16.2004, page 1 of 7