Parallel-Load 8-bit Shift Register
(Previous ADE-205-374 (Z))
This 8-bit serial shift register shifts data from QA to QH when clocked, Parallel inputs to each stage are enabled by a low
level at the Shift/Load Input. Also included is a gated clock input and a complementary output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit function.
Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the Shift/Load input
high enables the other clock input. Data transfer occurs on the positive going edge of the clock. Parallel loading is
inhibited as long as the Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the
register independent of the state of the clock.
• Outputs Source/Sink 24 mA
• Ordering Information
Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity)
HD74AC165FPEL SOP-16 pin (JEITA) FP-16DAV
EL (2,000 pcs/reel)
HD74AC165RPEL SOP-16 pin (JEDEC) FP-16DNV
EL (2,500 pcs/reel)
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Parallel F 4
Inputs G 5
13 C Parallel
Rev.2.00, Jul.16.2004, page 1 of 6