Quad. Bistable Latches
Oct 06, 2005
This latch is ideally suited for use as temporary storage for binary information processing, input/output, and indicator
units. Information present at the data (D) input is transferred to the Q output when the latch enable (LE) is high. The Q
output will follow the data input as long as the enable remains high. When the enable goes low, the information that
was present at the data input at the time the transition occurred is retained at the Q output unit the enable is permitted to
go high again.
• High Speed Operation: tpd (D to Q) = 12.5 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)
• Ordering Information
HD74HC75FPEL SOP-16 pin (JEITA)
HD74HC75RPEL SOP-16 pin (JEDEC)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
X L Q0
H : High level
L : Low level
X : Irrelevant
Q0, Q0 : Output level before the indicated steady state input conditions were established.
Rev.2.00, Oct 06, 2005 page 1 of 7