Dual J-K Flip-Flops (with Clear)
Oct 06, 2005
The flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse.
Each flip-flop has independent, J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and
accomplished by a low level on the input.
• High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)
• Ordering Information
HD74HC73FPEL SOP-14 pin (JEITA)
HD74HC73RPEL SOP-14 pin (JEDEC)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
L XXX LH
H L XX
H : High level
L : Low level
X : Irrelevant
Rev.2.00, Oct 06, 2005 page 1 of 7