Synchronous UP/Down Decade Counter
Synchronous Up/Down 4-bit binary Counter
Mar 30, 2006
This synchronous presettable decade counter features an internal carry look-ahead for cascading in high-speed counting
applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs
change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of
operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple-clock)
A buffered clock input triggers the four master-slave flip-flops on the rising (positive going) edge of the clock
waveform. This counter is fully programmable; that is, the outputs may each be preset to either level. The load input
circuitry allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low
level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two count enable inputs and a carry output. Both count enable
inputs (P and T) must be low to count. The direction of the count is determined by the level of the up/down input.
when the input is high, the counter counts up; when low, it counts down. Input T is fed forward to enable the carry
output. The carry output thus enabled will produce a low-level output pulse with a duration approximately equal to the
high portion of the QA output when counting up and approximately equal to the low portion of the QA output when
counting down. This low level overflow carry pulse can be used to enable successive cascaded stages. Transitions at
the enable P or T inputs are allowed regardless of the level of the clock input. All inputs are diode-clamped to minimize
transission-line effects, thereby simplifying system design. This counter features a fully independent clock circuit.
Changes at control inputs (enable P, Enable T, load, up/down) that will modify the operating mode have no effect until
clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely
by the conditions meeting the stable setup and hold times.
• High Speed Operation
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
HD74HC669FPEL SOP-16 pin (JEITA)
SOP-16 pin (JEDEC)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
Rev.2.00 Mar 30, 2006 page 1 of 10