Dual D-type Flip Flops with Preset and Clear
(Previous ADE-205-066C (Z))
Jul. 22, 2004
The HD74LVC74 has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The logic
level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset
and clear are independent of the clock and accomplished by a low level at the appropriate input. Low voltage and high-
speed operation is suitable at the battery drive product (note type personal computer) and low power consumption
extends the life of a battery for long time operation.
• VCC = 2.0 V to 5.5 V
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V to 5.5 V)
• Ordering Information
SOP–14 pin (JEITA) FP–14DAV
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
HL XXL H
HH↑ L L H
H H L X Q0 Q0
H H H X Q0 Q0
H H ↓ X Q0 Q0
H: High level
L: Low level
↓ : High to Low transition
↑ : Low to high transition
Q0: Level to Q before the indicated steady input conditions was established.
Note: 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if preset and
clear go high simultaneously.
Rev.4.00 Jul. 22, 2004 page 1 of 6