Dual 4-bit Binary Counters
(Previous ADE-205-276A (Z))
Jun. 28, 2004
The HD74LV393A contain two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by-
The HD74LV393A is incremented on the high to low transition (negative edge) of the clock input, and each has an
independent clear input. When clear is set high all four bits of each counter is set to a low level. This enables count
truncation and allows the implementation of divide-by-N counter configurations.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the
low-power consumption extends the battery life.
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
• Ordering Information
SOP–14 pin(JEITA) FP–14DAV
SOP–14 pin(JEDEC) FP–14DNV
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Rev.3.00 Jun. 28, 2004 page 1 of 10