Dual J-K Flip-Flops
(with Preset, Common Clear, and Common Clock)
• Ordering Information
Package Code Package
(Previous Code) Abbreviation
HD74LS78AFPEL SOP-14 pin (JEITA)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
K CK J
K CK J
L H X XX H L
H L X XX L H
L L X X X H* H*
H H ↓ L L Q0 Q0
H H ↓ HL H L
H H ↓ LH L H
H H ↓ HH
H H H X X Q0 Q0
Notes: H; high level, L; low level, X; irrelevant, ↓; transition from high to low level,
Q0; level of Q before the indicated steady-state input conditions were established.
Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established.
Toggle; each output changes to the complement of its previous level on each active transition indicated by ↓.
* This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (high) level.
Rev.3.00, Jul.22.2005, page 1 of 6